FPGA RTL Design Engineer

ALTEN; California (MO); On-site; USD 100,000 - 130,000; Full time

Job summary

ALTEN is looking for a PGA RTL Design Engineer in California, MO to design and develop hardware algorithms for advanced wireless communications. The ideal candidate will have 5+ years of experience in FPGA or ASIC design and be proficient in Verilog and System Verilog.

The role involves debugging complex FPGA designs and developing solutions for high-speed interfaces such as DDR4 and PCIe. Join our innovative team to contribute to cutting-edge wireless technologies!

Qualifications

• 5+ years of experience implementing complex digital designs in programmable logic using FPGA devices.
• Knowledge of FPGA architecture and advanced floor-planning techniques.
• Experience with Verilog, System Verilog and HDL-based design verification.

Responsibilities

• Design, develop, and debug hardware algorithms for an advanced wireless communications prototype.
• Implement complex digital designs and conduct regression testing.

Skills

FPGA design

Verilog

System Verilog

timing closure techniques

wireless standards (4G, 5G NR, Wi-Fi)

debugging complex designs

Education

MS in Electrical Engineering or Computer Engineering

Tools

Vivado

Modelsim

MATLAB

Job description

PGA RTL Design Engineer

design, develop, and debug hardware algorithms to help implement an advanced wireless communications prototype.

Job Description

• 5+ years implementing complex digital designs in programmable logic using FPGA devices, or equivalent experience in ASIC design
• Experience with Verilog, System Verilog and HDL-based design verification including regression testing.
• Thorough knowledge of FPGA architecture including experience with advanced floor‑planning and timing closure techniques.
• Experience with SoC bus interconnect protocols such as AXI4, streaming AXI and AHB.
• Experience with industry‑standard high‑speed interfaces such as DDR4, 10/40/100 GbE, PCIe and Interlaken.
• Experience with bring up and lab debugging of complex FPGA designs.
• Experience with wireless standards such as 4G, 5G NR or Wi‑Fi.
• Familiar with embedded software/firmware design, especially in complex debugging of on‑target SW/HW interaction.

Good to have

• MS Electrical Engineering, Computer Engineering, or a closely related field
• 8+ years implementing complex digital designs in programmable logic using FPGA devices, or equivalent experience in ASIC design
• Knowledge of FPGA design environments including Vivado, Modelsim, and MATLAB
• Experience using these techniques with Xilinx UltraScale/UltraScale+ FPGA families
• Familiarity with C, C++, or Python
• Experience working with IEEE-1588 PTP time synchronization and 802.3 Ethernet protocols