Verification Platform Engineer: High-Throughput DV Tooling

Apple, Inc.; Cupertino (CA); On-site; USD 150,000 - 225,000; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Employee stock purchase plan

Tuition reimbursement

Relocation assistance

Job summary

Apple, Inc. is seeking a Verification Platform Engineer in Cupertino to advance pre-silicon validation for Apple silicon. You will help build high-performance verification systems and optimize RTL simulation tooling within our Platform Architecture group.

The role emphasizes testbench design, infrastructure improvements, and collaboration with silicon engineering and EDA teams to accelerate DV workflows. Occasional travel within the US is expected.

Qualifications

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
• Experience with SystemVerilog and EDA tooling.
• Experience with software development (e.g., using C++) and scripting (e.g., Python).

Responsibilities

• Own engagements with silicon engineering groups to evaluate, integrate, and maintain high performance RTL simulation tooling.
• Modify testbench and design RTL for tool compatibility and simulation efficiency.
• Use internal and external EDA tools (e.g., RTL simulation tools, LEC, wave dumps, design libraries) to diagnose issues and explore design alternatives.
• Design and integrate infrastructure improvements for faster simulation turnaround after RTL changes.
• Partner closely (or embed) with internal teams for focused, high-impact engagements.
• Occasionally travel (approximately once a year) to collaborate with development groups within the US.

Skills

SystemVerilog

EDA tooling

C++

Python

UVM

DPI-C

Testbench architecture

Education

Bachelor's degree in Computer or Electrical Engineering

Master’s degree in Computer/Electrical Engineering (preferred)

Tools

RTL simulation tools

Logic Equivalence Checking (LEC)

wave dumps

design libraries

Job description

Apple, Inc. is seeking a Verification Platform Engineer in Cupertino to advance pre-silicon validation for Apple silicon. You will help build high-performance verification systems and optimize RTL simulation tooling within our Platform Architecture group.

The role emphasizes testbench design, infrastructure improvements, and collaboration with silicon engineering and EDA teams to accelerate DV workflows. Occasional travel within the US is expected.