Senior Silicon Engineer: AI-Driven IP & Verification

Cognichip; Redwood City (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Competitive compensation package, including equity participation

Collaborate with a high-caliber team

Work on foundational problems at the intersection of AI and hardware

A culture of innovation and impact

Job summary

A semiconductor technology company located in Redwood City is looking for a Senior Silicon Engineer. This role involves the technical ownership of logic design and validation for various functional blocks, requiring a strong background in CPU, IP, and SoC architecture. Candidates should have over 5 years' experience in design and validation, and proficiency in SystemVerilog and UVM. The position offers collaboration with a talented team and a competitive compensation package, including equity participation.

Qualifications

• 5+ years of experience in CPU, graphics, or SoC design and validation.
• Experience with logic design, timing closure, low-power design, and area optimization.
• Knowledge of verification methodologies and coverage analysis.

Responsibilities

• Technical ownership of logic design and validation of various functional blocks.
• Document microarchitecture specifications and drive reviews of specs.
• Develop validation content including UVM and SystemVerilog testbenches.

Skills

Strong knowledge of CPU, IP, and SoC architecture

Experience with logic design, synthesis

Experience with SystemVerilog and UVM

Experience with C/C++ and assembly

Strong cross-functional communication skills

Business-fluent English

Education

BS in Electrical Engineering or a related technical field

Job description

A semiconductor technology company located in Redwood City is looking for a Senior Silicon Engineer. This role involves the technical ownership of logic design and validation for various functional blocks, requiring a strong background in CPU, IP, and SoC architecture. Candidates should have over 5 years' experience in design and validation, and proficiency in SystemVerilog and UVM. The position offers collaboration with a talented team and a competitive compensation package, including equity participation.