Senior Verification Engineer — Emulation & UVM Expert

Hewlett Packard Enterprise Development LP; Sunnyvale (CA); Hybrid; USD 153,500 - 310,500; Full time

Job summary

Hewlett Packard Enterprise Development LP in California seeks a Senior Design Verification Engineer specializing in emulation-based verification to drive comprehensive verification strategies for complex digital designs before silicon tape-out.

You will develop and execute verification plans, build advanced UVM-based testbenches, run directed and constrained-random tests, and collaborate with design teams to manage corner cases and risk.

Qualifications

• Bachelor's degree in EE/CE/CS required.
• 5–8 years of design verification experience in digital/mixed-signal designs.
• Strong SystemVerilog and UVM proficiency.
• Hands-on with emulation-based verification platforms.

Responsibilities

• Develop and execute verification plans for IP-level and system-level designs.
• Build, maintain, and enhance UVM/SystemVerilog-based testbench environments including scoreboards, monitors, drivers, and coverage models.
• Develop and run directed and constrained-random test cases to achieve functional and code coverage goals.
• Set up, configure, and run designs on emulation platforms for system-level verification and performance validation.
• Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.
• Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.
• Develop and maintain assertion-based verification (SVA) to complement simulation and emulation efforts.
• Drive coverage closure and generate verification sign-off reports.
• Support software and firmware teams with early bring-up activities on emulation platforms.
• Continuously improve verification processes, flows, and infrastructure.

Skills

SystemVerilog

UVM

Emulation-based verification

Python

TCL scripting

Debugging

Coverage-driven verification

Waveform analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Cadence Palladium

Synopsys ZeBu

Mentor Veloce

JasperGold

Job description

Hewlett Packard Enterprise Development LP in California seeks a Senior Design Verification Engineer specializing in emulation-based verification to drive comprehensive verification strategies for complex digital designs before silicon tape-out.

You will develop and execute verification plans, build advanced UVM-based testbenches, run directed and constrained-random tests, and collaborate with design teams to manage corner cases and risk.