Design Verification Lead for Next-Gen SoC

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 174,000 - 352,500; Full time

Benefits offered by this job

Health benefits

Career development

Inclusive culture

Job summary

Hewlett Packard Enterprise is seeking a visionary Design Verification Manager to lead our silicon verification team. You will architect and execute advanced verification strategies for high-performance semiconductor products, bridging architectural complexity and flawless tape-outs.

The role requires hands-on technical authority, mentorship of senior staff, and a track record of scaling verification roadmaps across block, sub-system, and full-chip environments.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or related field.
• 10+ years of deep, hands-on pre-silicon ASIC/SoC design verification experience.
• 5+ years of engineering management or formal team leadership experience.
• Proven mastery building scalable UVM-compliant testbenches from scratch.

Responsibilities

• Team Leadership & Mentorship: manage, inspire, and grow a team of design verification engineers.
• Allocate resources across multiple parallel chip/block schedules.
• Define global verification strategies, infrastructure, and execution plans for complex SoCs and IP blocks.
• Own the testbench architecture from specifications to structural sign-off.
• Collaborate with Architecture, RTL Design, Physical Design, and Post-Silicon teams to meet tape-out milestones.

Skills

SystemVerilog

UVM

Formal verification

Leadership

Education

Bachelor’s degree in Electrical Engineering/Computer Science/Computer Engineering

Master’s degree (preferred)

Tools

Palladium

Zebu

Veloce

Job description

Hewlett Packard Enterprise is seeking a visionary Design Verification Manager to lead our silicon verification team. You will architect and execute advanced verification strategies for high-performance semiconductor products, bridging architectural complexity and flawless tape-outs.

The role requires hands-on technical authority, mentorship of senior staff, and a track record of scaling verification roadmaps across block, sub-system, and full-chip environments.