Hybrid ASIC Verification Engineer – SoC/UVM Expert

Hewlett Packard Enterprise Company; Sunnyvale (CA); Hybrid; USD 120,000 - 243,000; Full time

Benefits offered by this job

Health & Wellbeing

Personal & Professional Development

Unconditional Inclusion

Job summary

Hewlett Packard Enterprise is seeking an ASIC Verification Engineer for a hybrid role based in Sunnyvale, CA. You will own block-level verification efforts, develop advanced UVM environments, and collaborate across teams to ensure coverage closure and high-quality ASIC/SoC deliverables.

The ideal candidate has 3+ years of ASIC/SoC verification experience, strong SystemVerilog/UVM skills, and hands-on debugging with Cadence Xcelium, Synopsys VCS, or Mentor Questa.

Qualifications

• 3+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Skills

SystemVerilog

UVM

SoC verification

test planning

coverage analysis

SVA

Cadence Xcelium

Synopsys VCS

Mentor Questa

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise is seeking an ASIC Verification Engineer for a hybrid role based in Sunnyvale, CA. You will own block-level verification efforts, develop advanced UVM environments, and collaborate across teams to ensure coverage closure and high-quality ASIC/SoC deliverables.

The ideal candidate has 3+ years of ASIC/SoC verification experience, strong SystemVerilog/UVM skills, and hands-on debugging with Cadence Xcelium, Synopsys VCS, or Mentor Questa.