Senior Design Verification Engineer

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 153,500 - 310,500; Full time

Job summary

Hewlett Packard Enterprise Development LP in California seeks a Senior Design Verification Engineer specializing in emulation-based verification to drive comprehensive verification strategies for complex digital designs before silicon tape-out.

You will develop and execute verification plans, build advanced UVM-based testbenches, run directed and constrained-random tests, and collaborate with design teams to manage corner cases and risk.

Qualifications

• Bachelor's degree in EE/CE/CS required.
• 5–8 years of design verification experience in digital/mixed-signal designs.
• Strong SystemVerilog and UVM proficiency.
• Hands-on with emulation-based verification platforms.

Responsibilities

• Develop and execute verification plans for IP-level and system-level designs.
• Build, maintain, and enhance UVM/SystemVerilog-based testbench environments including scoreboards, monitors, drivers, and coverage models.
• Develop and run directed and constrained-random test cases to achieve functional and code coverage goals.
• Set up, configure, and run designs on emulation platforms for system-level verification and performance validation.
• Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.
• Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.
• Develop and maintain assertion-based verification (SVA) to complement simulation and emulation efforts.
• Drive coverage closure and generate verification sign-off reports.
• Support software and firmware teams with early bring-up activities on emulation platforms.
• Continuously improve verification processes, flows, and infrastructure.

Skills

SystemVerilog

UVM

Emulation-based verification

Python

TCL scripting

Debugging

Coverage-driven verification

Waveform analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Cadence Palladium

Synopsys ZeBu

Mentor Veloce

JasperGold

Job description

Senior Design Verification Engineer

This role is hybrid, requiring an average of 2 days per week at an HPE office. We seek a senior verification engineer with specialized knowledge in emulation‑based verification who can develop and execute comprehensive verification strategies for complex digital designs, ensuring functional correctness and performance targets before silicon tape‑out.

Responsibilities

• Develop and execute verification plans for IP‑level and system‑level designs.
• Build, maintain, and enhance UVM/SystemVerilog‑based testbench environments including scoreboards, monitors, drivers, and coverage models.
• Develop and run directed and constrained‑random test cases to achieve functional and code coverage goals.
• Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) for system‑level verification and performance validation.
• Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.
• Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.
• Develop and maintain assertion‑based verification (SVA) to complement simulation and emulation efforts.
• Drive coverage closure and generate verification sign‑off reports.
• Support software and firmware teams with early bring‑up activities on emulation platforms.
• Continuously improve verification processes, flows, and infrastructure.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 5–8 years of professional experience in design verification of digital/mixed‑signal designs.
• Strong proficiency in SystemVerilog and UVM methodology.
• Hands‑on experience with emulation‑based verification platforms (e.g., Cadence Palladium, Synopsys ZeBu, or Mentor Veloce).
• Solid understanding of digital design concepts including RTL design, synthesis constraints, and timing.
• Experience with constrained‑random verification, functional coverage, and code coverage‑driven methodologies.
• Proficiency in debugging complex hardware designs using simulation and emulation tools.
• Familiarity with scripting languages such as Python, Perl, or TCL for automation and flow development.
• Strong analytical and problem‑solving skills with excellent attention to detail.

Preferred Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with networking protocols such as Ethernet (10G/25G/100G/400G), TCP/IP, PCIe, or CXL.
• Knowledge of communication and interface protocols including AXI, AHB, APB, AMBA, I2C, SPI, or UART.
• Experience with formal verification tools and techniques (e.g., JasperGold, VC Formal).
• Familiarity with FPGA prototyping platforms and flows.
• Experience with power‑aware verification (UPF/CPF).
• Prior exposure to SoC‑level verification or full‑chip integration verification.
• Knowledge of processor architectures (ARM, RISC‑V, x86) and software‑driven verification techniques.
• Experience with continuous integration (CI) and regression management frameworks.
• Familiarity with AI/ML application and architectures and experience with creating Gen AI skills, marketplace, agentic applications, etc.
• Published work or patents in the area of design verification is a plus.

Salary

Annual salary USD 153,500–310,500 in California (base salary; variable incentives may also be offered).

Benefits

We offer a comprehensive suite of benefits that support physical, financial, and emotional wellbeing, including personal and professional development programs, and a culture of unconditional inclusion.

Job Details

Job: Engineering – Level: TCP_04

Equal Employment Opportunity

HPE is an Equal Employment Opportunity/Veteran/Disabled/LGBT employer and does not discriminate on the basis of race, gender, or any other protected category. All hiring decisions are based on qualifications, merit, and business need. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider qualified applicants with criminal histories.

E‑Verify

HPE is an E‑Verify employer. E‑Verify is an Internet‑based system that compares information from an employee's Form I‑9, Employment Eligibility Verification, to data from the U.S. Department of Homeland Security and Social Security Administration to confirm employment eligibility of all newly hired employees.