Lead Verification Engineer - Coherent IP & SoCs

Samsung Electronics America; Austin (TX); On-site; USD 151,000 - 252,000; Full time

Job summary

Samsung Electronics America in Austin seeks a Design Verification Engineer to verify System IP including coherent interconnects and caches for high-performance SoCs. You will architect and maintain reusable verification environments and testbenches, applying robust verification techniques across block- and top-level environments.

The role requires extensive SystemVerilog/UVM coding, ARM protocol knowledge, and collaboration with global teams to improve coverage, debug regressions, and advance

Qualifications

• 10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years with a Master’s, or 6+ years with a Ph.D.
• 8+ years in a design verification role building testbenches from scratch
• Proficiency in design verification of coherent interconnects; LPDDR memory controllers is a plus
• Proficiency with ARM protocols – CHI, AXI, ACElite, APB
• Strong coding skills in SystemVerilog, UVM
• Experience with Git version control, Unix/Perl scripting
• Formal verification skills are a plus
• Strong communication and collaboration skills in a global team environment

Responsibilities

• Verify System IP, including coherent interconnects and caches.
• Develop reusable verification environments and testbenches from scratch.
• Contribute to verification plans, coverage analysis, and debugging of regressions.
• Collaborate with design, SoC, physical design, and performance verification teams to enable bring-up across IP/SoC.

Skills

SystemVerilog

UVM

Testbench architecture

Coherent interconnects

ARM CHI/AXI/APB

Git

Unix scripting

Perl scripting

Formal verification

Strong communication

Education

Bachelor’s Degree in Computer Science/Engineering

Master’s Degree in CS/Engineering

Ph.D.

Tools

Git

Unix scripting

Perl scripting

Job description

Samsung Electronics America in Austin seeks a Design Verification Engineer to verify System IP including coherent interconnects and caches for high-performance SoCs. You will architect and maintain reusable verification environments and testbenches, applying robust verification techniques across block- and top-level environments.

The role requires extensive SystemVerilog/UVM coding, ARM protocol knowledge, and collaboration with global teams to improve coverage, debug regressions, and advance