Senior Validation Engineer, Processor & Power Management

Saicon; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Saicon in San Jose, CA is seeking an experienced engineer to join a highly technical team responsible for developing test plans and performing functional and electrical validation of new processor silicon interface features with a strong focus on power management.

The role involves writing comprehensive test plans, executing tests with oscilloscopes and logic analyzers, debugging issues, and providing input into platform definitions and designs used in silicon validation.

Qualifications

• 8–10 years of related experience in electrical/processor validation.
• Bachelor's or Master's degree in EE/CE; advanced degree a plus.
• Experience with development and execution of platform-level test plans and I/O interfaces.

Responsibilities

• Develop test plans and perform functional and electrical validation for processor silicon interface features with focus on power management.
• Execute tests on client processors using hardware/software validation tools (oscilloscopes, logic analyzers).
• Debug issues and provide input into platform definitions and designs used in silicon validation.
• Provide technical guidance and training to less experienced engineers and technicians.

Skills

Test plan development

Electrical validation

Functional validation

Debugging

Technical guidance

Written and verbal communication

Education

Bachelor's in Electrical Engineering or Computer Engineering

Master's degree (plus 8+ years experience)

Tools

Oscilloscopes

Logic analyzers

MS Windows

MS Office

Job description

Saicon in San Jose, CA is seeking an experienced engineer to join a highly technical team responsible for developing test plans and performing functional and electrical validation of new processor silicon interface features with a strong focus on power management.

The role involves writing comprehensive test plans, executing tests with oscilloscopes and logic analyzers, debugging issues, and providing input into platform definitions and designs used in silicon validation.