Senior SystemVerilog Verification Engineer (UVM)

Mirafra Technologies; United States; Remote; USD 120,000 - 160,000; Full time

Job summary

Mirafra Technologies seeks a verification engineer to develop and verify complex systems using SystemVerilog and UVM. You will contribute to the verification of digital designs by building testbenches, debugging issues, and documenting results.

The role requires a solid understanding of hardware design, strong debugging skills, and experience with simulation tools. Bachelor's is required; Master’s is a plus, with a collaborative team environment in a technology-forward company.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• Master's degree is a plus.
• Proficiency in SystemVerilog and UVM required.
• Strong understanding of digital design concepts.
• Experience with simulation tools and methodologies.

Responsibilities

• Develop and implement testbenches using SystemVerilog and UVM.
• Collaborate with design engineers to understand specifications and requirements.
• Perform functional verification of digital designs.
• Debug and troubleshoot issues in the verification environment.
• Document verification plans and results.

Skills

SystemVerilog

UVM

Digital design concepts

Simulation tools

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree is a plus

Job description

Mirafra Technologies seeks a verification engineer to develop and verify complex systems using SystemVerilog and UVM. You will contribute to the verification of digital designs by building testbenches, debugging issues, and documenting results.

The role requires a solid understanding of hardware design, strong debugging skills, and experience with simulation tools. Bachelor's is required; Master’s is a plus, with a collaborative team environment in a technology-forward company.