Senior Systems Engineer - High-Speed SerDes & AI Optimization

Qualcomm; Toronto (OH); On-site; USD 65,000 - 101,000; Full time

Job summary

Qualcomm Canada ULC is seeking an experienced ASIC design and verification engineer to run behavioral channel simulations and model complex analog blocks for high-speed SERDES systems. You will contribute to architecture definitions for SERDES links across multiple standards and develop tools to accelerate design and debugging in collaboration with the analog/validation teams.

The role requires strong MATLAB, C/C++, Python, Tcl, and Perl skills, with experience in PCIe and/or Ethernet SerDes

Qualifications

• Bachelor's degree in Science, Engineering, or related field and 6 years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 5 years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4 years of ASIC design, verification, validation, integration, or related work experience.
• Strong programming skills in MATLAB, C/C , scripting skills in Python, Tcl, Perl.
• Experience working with PCIe and/or Ethernet Serdes specifications.

Responsibilities

• Run behavioral channel simulation and analysis of high-speed wireline analog/DSP SERDES for 100G PAM4 standards.
• Model complex analog blocks, such as Transmitter, FFE, CTLE, DFE, and CDRs
• Contribute to Architecture definition for SERDES links for several standards
• Develop and deploy tools for analog / validation teams to speed up design and debug
• Work with state-of-the-art optimization and machine learning algorithms for chip optimization
• Contribute to and help develop adaptation algorithms for a variety of equalization techniques
• Perform sensitivity analysis and regression simulations for various link conditions
• Work with internal silicon engineering team to help perform system performance correlation between behavior models and silicon

Skills

SERDES modelling

MATLAB

C/C++

Python

Tcl

Perl

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

IBIS-AMI

Job description

Qualcomm Canada ULC is seeking an experienced ASIC design and verification engineer to run behavioral channel simulations and model complex analog blocks for high-speed SERDES systems. You will contribute to architecture definitions for SERDES links across multiple standards and develop tools to accelerate design and debugging in collaboration with the analog/validation teams.

The role requires strong MATLAB, C/C++, Python, Tcl, and Perl skills, with experience in PCIe and/or Ethernet SerDes