Senior Substrate Architecture & Process Lead

Advanced Micro Devices, Inc.; Austin (TX); On-site; USD 150,000 - 210,000; Full time

Job summary

AMD, based in Austin, Texas, seeks a senior engineer to lead substrate architecture and design rule development for next‑gen packaging. You will define requirements and work with architects, silicon teams, and suppliers to co‑optimize performance, yield, reliability and cost.

The ideal candidate brings deep expertise in substrate stack‑up, DFY/DFM, and scalable design methodologies for 2.5D/chiplet packaging, delivering high‑performance compute solutions.

Qualifications

• Experience in advanced packaging, substrate design, or package technology development.
• Deep expertise in substrate stack-up architecture, routing technologies, HDI design, and advanced package substrates.
• Extensive experience developing substrate design rules for manufacturing and reliability.
• Strong understanding of signal integrity, power integrity, and package electrical performance.
• Experience with design-for-manufacturability, design-for-yield, and design-process co-optimization.
• Strong understanding of substrate manufacturing processes and process integration principles.
• Experience supporting advanced package architectures including chiplet, 2.5D, and heterogeneous integration solutions.
• Proven ability to influence technical direction across multiple organizations and suppliers.
• Demonstrated success presenting strategy and technical roadmaps to senior leadership.

Responsibilities

• Define substrate technology requirements and design roadmaps for future AMD products.
• Develop substrate design rules, stack-up methodologies, routing architectures, and technology guidelines.
• Establish scalable design infrastructures supporting future substrate technology nodes.
• Drive substrate architecture development across line/space scaling, via technologies, and advanced package integration.
• Lead design-process co-optimization activities across substrate manufacturing technologies.
• Define process-aware design methodologies that improve manufacturability and reduce development risk.
• Collaborate with suppliers to establish process windows, design limitations, and technology capabilities.
• Drive technology readiness assessments for emerging substrate platforms.
• Develop design methodologies that maximize manufacturing yield and process robustness.
• Identify systematic design sensitivities impacting supplier yield and manufacturing cost.
• Define design guidelines and best practices that improve technology scalability.
• Drive design-related yield learning and continuous improvement initiatives.
• Lead substrate reliability strategy and design rule development for mechanical and electrical robustness.
• Develop reliability-aware design guidelines for advanced package applications.
• Partner with reliability teams to understand failure mechanisms and translate learning into improved design requirements.
• Drive technology qualification and design robustness assessments.
• Drive substrate architecture solutions for signal integrity, power integrity, and high-speed package performance.
• Collaborate with package and silicon architects to optimize electrical performance across the package system.
• Develop technology solutions supporting future AI, HPC, and heterogeneous integration products.
• Balance performance requirements with manufacturability, reliability, and cost objectives.
• Influence substrate supplier technology roadmaps and capability development.
• Evaluate emerging substrate technologies and manufacturing innovations.
• Establish design requirements and technical targets for development partners.
• Build strategic technology partnerships across the substrate ecosystem.
• Demonstrated success presenting strategy and technical roadmaps to senior leadership.

Skills

Substrate design

Design rules

Process integration

Design for Yield

Reliability

Performance optimization

Supplier leadership

HDI design

2.5D packaging

Chiplet packaging

Job description

AMD, based in Austin, Texas, seeks a senior engineer to lead substrate architecture and design rule development for next‑gen packaging. You will define requirements and work with architects, silicon teams, and suppliers to co‑optimize performance, yield, reliability and cost.

The ideal candidate brings deep expertise in substrate stack‑up, DFY/DFM, and scalable design methodologies for 2.5D/chiplet packaging, delivering high‑performance compute solutions.