Lead Static Timing Analysis Engineer

ZealHire Inc.; Austin (TX); Hybrid; USD 140,000 - 210,000; Full time

Job summary

ZealHire Inc. in Austin, TX, seeks a highly experienced Senior/Lead Static Timing Analysis (STA) Engineer to drive timing closure for complex ASIC/SoC designs.

The role requires ownership of full-chip and block-level STA from early implementation to final signoff and close collaboration with RTL, synthesis, physical design, and signoff teams. You will develop and validate timing constraints (SDC, clocks, IO), analyze setup/hold across MCMM/PVT corners, and mentor junior engineers while guiding

Qualifications

• 12–18 years of experience in semiconductor/ASIC design with significant hands-on STA experience.
• Strong understanding of static timing analysis and timing signoff methodologies.
• Expert knowledge of Synopsys PrimeTime or equivalent STA tools.
• Strong expertise in SDC constraints, clock definitions, timing exceptions, and MCMM analysis.
• Deep understanding of setup/hold analysis, clock timing, OCV/AOCV/POCV, CPPR, SI/crosstalk, and variation effects.

Responsibilities

• Own and drive full-chip and block-level STA from early implementation through final timing signoff.
• Develop, review, and validate timing constraints including SDC, clocks, generated clocks, IO constraints, exceptions, and modes/corners.
• Perform detailed setup/hold timing analysis across MCMM/PVT corners.
• Drive timing closure and identify root causes of critical timing violations.
• Analyze and debug issues related to clock skew, OCV/AOCV/POCV, SI/crosstalk, derates, uncertainty, and variation.
• Work closely with physical design teams to resolve timing issues through optimization of placement, CTS, routing, buffering, sizing, and ECOs.
• Review timing reports and identify opportunities for performance, power, and area optimization.
• Support timing signoff methodology development, flow automation, and quality improvements.
• Partner with RTL and synthesis teams to identify constraint, logic, and architectural issues impacting timing.
• Participate in signoff reviews and provide technical guidance on timing risks and closure status.
• Mentor junior and senior engineers and provide technical leadership on complex timing problems.
• Collaborate with cross-functional teams to establish schedules, milestones, and timing closure strategies.

Skills

Cross-functional collaboration

Leadership

Problem solving

Mentorship

Tools

Synopsys PrimeTime

Tcl scripting

Python

Perl

Job description

USC/GC/GC-EAD/H4-EADNeed LinkedIn, VISA DL

• Full-chip STA & timing signoff
• SDC, MCMM, OCV/AOCV/POCV, SI
• PrimeTime + Tcl (Python/Perl a plus)
• 12–18 yrs ASIC/SoC

ONSITE POSITION

Video interview

About the job We are seeking a highly experienced Senior/Lead Static Timing Analysis (STA) Engineer to drive timing closure and signoff for complex, high-performance semiconductor designs. The ideal candidate will have deep expertise in STA methodologies, timing constraints, signoff flows, and cross-functional timing closure across advanced process nodes. This role requires strong technical ownership, the ability to debug complex timing issues, and close collaboration with RTL, synthesis, physical design, clocking, and signoff teams. Key Responsibilities • Own and drive full-chip and block-level STA from early implementation through final timing signoff. • Develop, review, and validate timing constraints including SDC, clocks, generated clocks, IO constraints, exceptions, and modes/corners. • Perform detailed setup/hold timing analysis across MCMM/PVT corners. • Drive timing closure and identify root causes of critical timing violations. • Analyze and debug issues related to clock skew, OCV/AOCV/POCV, SI/crosstalk, derates, uncertainty, and variation. • Work closely with physical design teams to resolve timing issues through optimization of placement, CTS, routing, buffering, sizing, and ECOs. • Review timing reports and identify opportunities for performance, power, and area optimization. • Support timing signoff methodology development, flow automation, and quality improvements. • Partner with RTL and synthesis teams to identify constraint, logic, and architectural issues impacting timing. • Participate in signoff reviews and provide technical guidance on timing risks and closure status. • Mentor junior and senior engineers and provide technical leadership on complex timing problems. • Collaborate with cross-functional teams to establish schedules, milestones, and timing closure strategies. Required Qualifications • 12–18 years of experience in semiconductor/ASIC design with significant hands-on STA experience. • Strong understanding of static timing analysis and timing signoff methodologies. • Expert knowledge of Synopsys PrimeTime or equivalent STA tools. • Strong expertise in SDC constraints, clock definitions, timing exceptions, and MCMM analysis. • Deep understanding of setup/hold analysis, clock timing, OCV/AOCV/POCV, CPPR, SI/crosstalk, and variation effects. • Experience with advanced-node timing closure and complex SoC designs. • Strong understanding of synthesis, physical design, CTS, routing, and ECO flows. • Proficiency in Tcl scripting; Python or Perl experience is a plus. • Strong analytical and problem-solving skills. • Excellent communication and cross-functional collaboration skills.

$000,000 – $000,000 Salary range is not shown on the candidate portal

Apply before Oct 31, 2026 — don't miss this opportunity!