Senior Standard Cell Design Engineer – End-to-End PPA

Intel; Santa Clara (CA); Hybrid; USD 122,000 - 232,000; Full time

Job summary

Intel's Foundry Standard Cell team in Santa Clara seeks a Senior Design Engineer to join our growing group. You will design leading-edge experiments to develop, characterise, and test standard cells, enabling customers with robust solutions.

You will own end-to-end flows for physical design, optimize PPA, and collaborate with multiple teams to validate designs. A Bachelor's in engineering and 2+ years in related work are expected, with strong communication skills.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field.
• 2+ years' experience in standard cell layout, abstract modelling, characterisation, or ASIC design and verification.
• Experience using one or more of the following tools: Cadence Virtuoso, Synopsys/ Cadence tool suite.

Responsibilities

• Defines, implements, characterises, and validates design solutions to meet design requirements for power, performance, area (PPA), manufacturability, and cost.
• Capable of implementing all aspects of the physical design flow, including standard cell circuit, layout, extraction, characterisation, and optimisation of timing, congestion, power, signal integrity, and reliability to achieve goals.
• Collaborates closely with all standard cell collateral to understand design requirements and develop robust implementation and validation strategies.
• Reviews and validates work to ensure compliance with design, manufacturing, and quality requirements.
• Fast turn‑around experiments - devising experiments, running them end to end, and guiding data driven decisions across multiple audiences (peer working groups, management, and technical leaders).
• Run end‑to‑end flows to generate, validate, and release custom standard cell collateral per on demand requests.

Skills

Standard cell layout

Standard cell abstract modelling

Standard cell characterisation

ASIC design and verification

Education

Bachelor's degree in Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field

Tools

Cadence Virtuoso

Synopsys Custom Compiler

Cadence Abstract Generator

Synopsys PrimeLib

Cadence Liberate

Synopsys Fusion Compiler

Cadence Innovus

Cadence Tempus

Synopsys PrimeTime

Synopsys HSpice

Synopsys StarRC

Synopsys ICV

Cadence Pegasus

Siemens Calibre

Job description

Intel's Foundry Standard Cell team in Santa Clara seeks a Senior Design Engineer to join our growing group. You will design leading-edge experiments to develop, characterise, and test standard cells, enabling customers with robust solutions.

You will own end-to-end flows for physical design, optimize PPA, and collaborate with multiple teams to validate designs. A Bachelor's in engineering and 2+ years in related work are expected, with strong communication skills.