Senior/Staff Engineer, ASIC Design

Black Sesame Technologies Inc; San Jose (CA); On-site; USD 140,000 - 170,000; Full time

Job summary

Black Sesame Technologies Inc. is seeking an experienced RTL/SoC engineer to develop micro-architecture for High Speed IO and lead RTL design, verification, and integration.

The role requires a Master’s degree and 5+ years of experience in HDL languages (Verilog/SystemVerilog) and hands-on work with PCIe, Die-to-Die and Ethernet interfaces. You will collaborate with architecture and software teams to push the next generation of AI silicon, contributing to timing, area and power optimization and

Qualifications

• Master's degree in Electrical/Electronics/CE with 5+ years of experience.
• Fluent with HDL languages Verilog/SystemVerilog.
• Experience with High Speed IO (PCIe, Die-to-Die, Chip-to-Chip, Ethernet) and C/C++.

Responsibilities

• Develop micro-architecture for High Speed IO design.
• RTL design, verification and integration.
• Synthesis and optimization for timing, area and power.
• Module and top-level documentation.
• Collaborate with architecture and software teams for next-gen silicon.

Skills

HDL languages Verilog/SystemVerilog

C/C++

High Speed IO

RTL design/verification

Education

Master's degree in Electrical/ Electronics/ CE

Job description

Founded in 2016 and listed on the Hong Kong Stock Exchange (HKEX: 2533), Black Sesame Technologies is a leading provider of AI system-on-chip solutions. Our mass-produced AI chips are deployed across the automotive and robotics markets, delivering high-performance, automotive-grade computing solutions at scale. As we develop our next generation of AI inference accelerators, we are rapidly expanding our R&D teams in Singapore and the United States. Join us and help build the foundational technologies powering the future of intelligent machines.

Responsibilities

• 1. Develope micro-architecture for High Speed IO design
• 2. RTL design, verification and integration
• 3. Synthesis and optimize for timing, area and power
• 4. Module and top-level documentation
• 5. Work with architecture and software teams to develop next-generation silicon.

Basic Qualifications

• 1. Master's degree and above in Electrical/Electronics/Computer Engineering， 5+ years experience.
• 2. Fluent with HDL languages(Verilog, SystemVerilog)
• 3. Experience in High Speed IO such as PCIE, Die to Die, Chip to Chip, Ethernet and etc
• 4. Familiar with software languages C/C++