Lead ASIC Design Engineer

Oho Group; San Jose (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Oho Group in the San Francisco Bay Area is seeking a Lead ASIC Design Engineer with 10+ years of ASIC/SoC experience to own RTL design and microarchitecture for high-performance AI accelerator solutions.

You will collaborate with verification, architecture, software and system teams, work on PCIe/CXL/UCIe interconnects and memory systems, and contribute across the silicon development lifecycle from early stage development.

Qualifications

• 10+ years of ASIC/SoC design experience with hands-on RTL development.
• Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
• Familiarity with PCIe, CXL or UCIe interconnect technologies.

Responsibilities

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and protocols.
• Define and review microarchitectural specs and translate to synthesizable RTL.
• Collaborate with architecture, verification, software and system teams throughout silicon development cycle.

Skills

RTL design

Microarchitecture

SoC design

Interconnects

PCIe / CXL / UCIe

GPU/AI accelerator experience

Education

BS, MS or PhD in Electrical Engineering / Computer Engineering / CS

Tools

PCIe

CXL

UCIe

HBM

Job description

Lead ASIC Design Engineer – San Francisco Bay Area – AI Accelerator Startup

A fast-moving startup in the Bay Area is looking for ASIC design engineers with strong experience across IP, architecture and microarchitecture within the AI accelerator space. Offering high ownership from day one and the opportunity to work with a world-class team of industry leaders from the top semiconductor companies, this is an exciting role for someone who wants to be a part of something from an early stage.

Key Responsibilities

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and associated protocols.
• Define and review microarchitectural specifications and translate them into robust, synthesizable RTL.
• Work closely with verification engineers on design validation, debugging and performance analysis.
• Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.

What We're Looking For

• 10+ years of ASIC/SoC design experience, with substantial hands-on RTL development.
• Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
• Familiarity with technologies such as PCIe, CXL or UCIe.
• Experience working on GPUs, AI accelerators, CPUs, TPUs is highly desirable.
• Experience with HBM, memory controllers or coherent fabrics is a strong plus.

Education

BS, MS or PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field.