Senior Staff Digital Design Engineer

Credo; San Jose (CA); On-site; USD 160,000 - 250,000; Full time

Job summary

Credo is seeking a Senior Staff PHY RTL Design Engineer at its San Jose, CA headquarters to lead RTL architecture, design, implementation and verification of SerDes DSP blocks for high-performance networking and data center products.

The ideal candidate has strong RTL development experience with SystemVerilog and a solid background in high-speed SerDes architectures, ASIC flows, and debugging. Onsite role with comprehensive compensation and bonus eligibility.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field, with eight or more years of digital design experience (or equivalent expertise for senior candidates).
• Strong RTL development skills using SystemVerilog, including fixed-point arithmetic RTL implementation.
• Experience designing high-speed communication or DSP hardware.
• Experience with the ASIC development flow (e.g., Lint, CDC/RDC, synthesis, timing analysis) and familiarity with EDA tools from Synopsys, Cadence, or Siemens.
• Strong debugging and problem-solving skills.

Responsibilities

• Define RTL micro-architecture for digital PHY and SerDes DSP functions.
• Develop synthesizable RTL for DSP blocks (FFE, DFE, adaptive equalization, CDR loops).
• Optimize designs for performance, power, area, and latency.
• Verify DSP modules and debug functional issues; support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
• Analyze silicon bring-up data with validation teams to resolve issues, and support PHY integration and system-level debugging.

Skills

SystemVerilog

RTL development

DSP hardware

Synchronous design

Education

Electrical/ECE degree

Tools

Synopsys

Cadence

Siemens

Job description

About the role

Team Credo is looking for a Senior Staff PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking, AI, data center, and high-performance computing products. The ideal candidate possesses strong digital design fundamentals, hands-on RTL development experience, and a good understanding of high-speed SerDes architecture. This position will be onsite at our San Jose, CA HQ.

Base salary range

Base salary range is $160,000 - $250,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

Why Credo

• Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what's next. Our technology powers the most reliable and energy-efficient connections around the world - and our team powers new products and markets that come next.

Qualifications

Basic Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field, with eight or more years of digital design experience (or equivalent expertise for senior candidates).
• Strong RTL development skills using SystemVerilog, including fixed-point arithmetic RTL implementation.
• Experience designing high-speed communication or DSP hardware.
• Experience with the ASIC development flow (e.g., Lint, CDC/RDC, synthesis, timing analysis) and familiarity with EDA tools from Synopsys, Cadence, or Siemens.
• Strong debugging and problem-solving skills.

Preferred Qualifications

• Experience with high-speed SerDes standards such as PCIe and Ethernet, and an understanding of SerDes receiver and transmitter architectures.
• Understanding of DSP algorithms (e.g., LMS adaptation, timing recovery), with MATLAB or C/C++ modeling experience.
• Familiarity with Python or other scripting languages.
• Knowledge of mixed-signal PHY architecture and analog/digital interfaces, including experience with mixed-signal PHY simulations.
• Experience supporting silicon bring-up and post-silicon validation, with exposure to advanced process nodes (7nm, 5nm, 3nm, or beyond).

Responsibilities

• Define RTL micro-architecture for digital PHY and SerDes DSP functions.
• Develop synthesizable RTL for DSP blocks (FFE, DFE, adaptive equalization, CDR loops), working with system architects and algorithm teams to translate DSP algorithms into RTL.
• Optimize designs for performance, power, area, and latency.
• Verify DSP modules and debug functional issues; support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
• Analyze silicon bring-up data with validation teams to resolve issues, and support PHY integration and system-level debugging.

About Credo

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.

Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, gender identity, sexual orientation, pregnancy, marital status, national origin, ethnicity, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [e-mail].

Salary

160000 - 250000 USD (yearly)