Sr. Design Verification Engineer

Credo; San Jose (CA); On-site; USD 138,000 - 218,000; Full time

Job summary

Credo is seeking a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through rigorous verification. You will develop verification plans, build scalable testbenches, and write SV-UVM sequences while collaborating with RTL designers and firmware teams.

The role emphasizes PCIe verification, RTL design proficiency, and strong debugging. You will contribute to flexible verification workflows and drive silicon quality across HW/SW interfaces.

Qualifications

• BS/MS in Electrical Engineering or Computer Engineering with 7+ years in RTL and SV-UVM verification.
• PCIe verification experience with gate-level and firmware-based simulation.
• Proficiency in RTL design and computer architecture concepts.
• Strong debugging, problem-solving, and analytical skills.

Responsibilities

• Develop verification and test plans; build reusable SV-UVM testbenches and sequences.
• Verify PCIe subsystems and interfaces (I2C/I3C/SMBus/UART/SPI) at block/subsystem levels.
• Write assertions, checkers, and coverage; analyze gaps and drive closure.
• Build firmware-based simulations in C to mirror FW behavior for HW/SW verification.
• Automate flows with Python; collaborate with AEs and FW teams on DV findings.

Skills

SV-UVM

RTL verification

PCIe verification

Debugging

Problem solving

Python scripting

FW interaction

Education

BS/MS in Electrical or Computer Engineering

Job description

About the role

Team Credo is seeking a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through rigorous verification. You'll develop and execute verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.

About the role

Team Credo is seeking a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through rigorous verification. You'll develop and execute verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.

Base salary range

$138,000 - $218,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

Why Credo

• Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what's next. Our technology powers the most reliable and energy-efficient connections around the world - and our team powers new products and markets that come next.

Qualifications

Basic Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or a related field, with seven or more years of experience in RTL and functional verification using SV-UVM.
• PCIe verification experience, plus experience with gate-level simulation and firmware-based simulation.
• Proficiency in RTL design and computer architecture concepts.
• Strong debugging, problem-solving, and analytical skills.

Preferred Qualifications

• Background in high-speed connectivity solutions (PCIe/CXL, SerDes, optical DSP).
• Experience working across HW/SW boundaries and with application engineering/firmware teams.
• PHY verification experience.

Responsibilities

• Understand design intent and develop comprehensive verification and test plans; develop reusable, scalable SV-UVM testbenches and write test sequences.
• Verify PCIe subsystems and other interfaces (I2C/I3C/SMBus/CPU/UART/SPI) at block and subsystem levels (e.g., PHY, controller).
• Write assertions, checkers, and coverage, analyze functional and code coverage gaps, and drive closure.
• Build firmware-based simulations in C that mirror or approximate real FW behavior to validate HW/SW interactions; reproduce silicon failures in simulation and perform deep debug to root cause.
• Automate flows with Python/Perl/Shell scripting; collaborate with AEs and FW teams on debug, feature implementation, and spec contributions driven by DV findings.

About Credo

Credo's mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.

Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, gender identity, sexual orientation, pregnancy, marital status, national origin, ethnicity, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate your website or complete the application process, email [e-mail].

Salary

130000 - 160000 USD (yearly)