Digital Design Engineering Intern

Credo; San Jose (CA); On-site; USD 25,003 - 35,610; Part time

Benefits offered by this job

Meaningful projects

Competitive compensation

Growth opportunities

Job summary

A technology company in California is seeking a motivated Digital Design Engineering Intern to join the Internal R&D team. In this internship, you will collaborate with engineers to develop high-speed SerDes and DSP-based architectures. Responsibilities include implementing RTL modules, developing behavioral models, and supporting verification efforts. Candidates should be pursuing a degree in Electrical Engineering or related fields, with skills in SystemVerilog, MATLAB, and Python. This role offers an hourly pay of $22, starting in May/June.

Qualifications

• Pursuing a degree in Electrical Engineering or Computer Engineering.
• Experience in digital design, DSP, or communication systems.
• Proficiency in SystemVerilog, MATLAB, Python, or C/C++.

Responsibilities

• Implement and verify RTL modules for SerDes and DSP.
• Collaborate with analog teams on high-speed transceiver designs.
• Develop behavioral models for system components.

Skills

SystemVerilog/Verilog

MATLAB

Python

C/C++

Analytical skills

Problem-solving skills

Education

Currently pursuing a BS, MS, or PhD in Electrical Engineering or related field

Tools

EDA flows

FPGA prototyping

Simulation tools

Job description

Credo is seeking a motivated and detail-oriented Digital Design Engineering Intern to join our Internal R&D team. You will collaborate closely with experienced system, design, and applications engineers to help develop high-speed SerDes and DSP-based digital architectures that power next-generation connectivity and compute platforms. The role spans RTL design, modeling, verification, and performance analysis of advanced mixed-signal systems. We’re looking for someone with a solid foundation in digital/ASIC design, familiarity with communication systems and DSP concepts, and a collaborative, eager-to-learn mindset.

Hourly Pay is $22.

Summer Internship will start May/June.

Why Credo

• Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.

Responsibilities

• Implement, optimize, and verify RTL modules for SerDes datapaths, DSP blocks, and supporting digital logic.
• Work with analog and mixed-signal teams on co-design of high-speed transceivers, including equalization, adaptation, and calibration logic.
• Develop behavioral models in SystemVerilog, MATLAB, or Python for system components such as PLLs, CDRs, and equalizers.
• Contribute to verification efforts, including testbench development, constrained-random testing, and coverage analysis.
• Support synthesis, linting, timing closure, and power/performance optimization.
• Analyze simulation results, characterize system performance, and document design decisions and findings.

Qualifications

• Currently pursuing a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Coursework or project experience in digital design, DSP, communication systems, or high-speed I/O.
• Proficiency with SystemVerilog/Verilog, MATLAB, Python, or C/C++.
• Understanding of SerDes architectures, equalization techniques, or link adaptation is a plus.
• Experience with FPGA prototyping, simulation tools, or EDA flows is beneficial.
• Strong analytical and problem-solving skills, with the ability to work effectively in cross-functional teams.
• Clear and effective verbal and written communication skills.

Preferred Qualifications

• Familiarity with common analog circuit blocks and their behavior.
• Knowledge of high-speed SerDes protocols such as Ethernet, PCIe, USB, or DDR.
• Experience with system bring-up of high-speed serial links.
• Understanding of SerDes architectures, equalization techniques, or link adaptation.
• Experience with FPGA prototyping, simulation tools, or EDA flows.
• Strong data processing and analytical capabilities.
• Understanding of SerDes design concepts including CDR, equalization, and adaptation techniques.
• Exposure to ADC-based links, optical link architectures, or related technologies.
• Demonstrated ability to troubleshoot complex problems and collaborate effectively with diverse engineering teams.

About Credo

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.

Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [e-mail].