Senior Staff Digital Control Verification Engineer

IC Resources; Austin (TX); Hybrid; USD 140,000 - 210,000; Full time

Benefits offered by this job

Hybrid in Austin, TX

Relocation and visa sponsorship

Strong base and annual bonus

Job summary

IC Resources is seeking a Senior Staff Digital Engineer in Austin, TX to lead verification of digital control loops for advanced power products used in AI and high-performance computing. You will own the verification framework from RTL through silicon and mentor engineers.

You will develop test plans, automate regression using SystemVerilog, Python and MATLAB, model analog behavior around digital designs, and drive pass/fail criteria across models, RTL, bench, and silicon.

Qualifications

• Hands-on SystemVerilog-based verification experience.
• Strong understanding of control loop fundamentals and DSP concepts.
• Experience building verification tools or test frameworks used by engineers.

Responsibilities

• Verify digital control loops in RTL: stability, frequency response, transient behavior and corner cases.
• Turn internal loop analysis tools into a production test framework used across the group.
• Build test plans, coverage and regression automation in SystemVerilog, Python and MATLAB.
• Model the analog behavior around the digital design so the loop can be tested before silicon.
• Correlate results across models, RTL simulation, bench and silicon.
• Work with design, firmware and validation engineers to turn requirements into pass/fail criteria.

Skills

SystemVerilog verification

Control theory

DSP concepts

Python for automation

MATLAB

Tools

UVM

AMS

Real Number Modeling

Job description

IC Resources is seeking a Senior Staff Digital Engineer in Austin, TX to lead verification of digital control loops for advanced power products used in AI and high-performance computing. You will own the verification framework from RTL through silicon and mentor engineers.

You will develop test plans, automate regression using SystemVerilog, Python and MATLAB, model analog behavior around digital designs, and drive pass/fail criteria across models, RTL, bench, and silicon.