Senior Digital Verification Engineer – High-Speed AI SoCs

EF; Austin (TX); On-site; USD 130,000 - 210,000; Full time

Benefits offered by this job

Equity & Ownership

Proximity Bonus (Living-Local)

Retirement Benefits

Job summary

OLIX in Austin is seeking Senior/Staff Digital Verification Engineers to own verification of high-speed data-processing silicon. You will drive end-to-end verification from algorithms to RTL and bring-up, using SystemVerilog/UVM, formal methods, and Python/MATLAB toolchains.

Ideal candidates have 5+ years in ASIC/SoC verification, experience with GHz-class designs, and strong collaboration across digital, optical, and software teams.

Qualifications

• 5+ years of hands-on digital verification experience in high‑performance ASICs or SoCs.
• Ownership of verification for at least one complex block or subsystem processing continuous real‑time data streams.
• Proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (UVM, CocoTB).
• Experience with GHz clock domains, CDC/RDC analysis, and RTL/formal verification flows.

Responsibilities

• Own end-to-end verification of high-throughput digital pipelines for multi-GSPS input rates.
• Develop and maintain verification environments using SystemVerilog/UVM with constrained-random testing and coverage closure.
• Define and implement assertion-based strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance.
• Apply formal verification techniques to complement simulation and accelerate bug discovery.
• Model and validate algorithms in MATLAB/Simulink or Python, ensuring equivalence from models to RTL and gate-level sign-off.
• Support FPGA prototyping and silicon bring-up with targeted testcases and debug strategies.
• Collaborate across digital, optical, mixed-signal and software teams for correct integration.
• Analyze verification results to identify root causes and drive design fixes to improve efficiency.
• Contribute to verification methodology, documentation, and reviews; mentor junior engineers.

Skills

Digital verification

SystemVerilog/UVM

GHz-class clock domain verification

Formal verification techniques

Python/NumPy modelling

Tools

SystemVerilog

UVM

CocoTB

MATLAB/Simulink

Python

Job description

OLIX in Austin is seeking Senior/Staff Digital Verification Engineers to own verification of high-speed data-processing silicon. You will drive end-to-end verification from algorithms to RTL and bring-up, using SystemVerilog/UVM, formal methods, and Python/MATLAB toolchains.

Ideal candidates have 5+ years in ASIC/SoC verification, experience with GHz-class designs, and strong collaboration across digital, optical, and software teams.