Senior Digital Design Engineer

IC Resources; Austin (TX); Hybrid; USD 140,000 - 210,000; Full time

Benefits offered by this job

Hybrid in Austin, TX

Relocation and visa sponsorship

Strong base and annual bonus

Job summary

IC Resources is seeking a Senior Staff Digital Engineer in Austin, TX to lead verification of digital control loops for advanced power products used in AI and high-performance computing. You will own the verification framework from RTL through silicon and mentor engineers.

You will develop test plans, automate regression using SystemVerilog, Python and MATLAB, model analog behavior around digital designs, and drive pass/fail criteria across models, RTL, bench, and silicon.

Qualifications

• Hands-on SystemVerilog-based verification experience.
• Strong understanding of control loop fundamentals and DSP concepts.
• Experience building verification tools or test frameworks used by engineers.

Responsibilities

• Verify digital control loops in RTL: stability, frequency response, transient behavior and corner cases.
• Turn internal loop analysis tools into a production test framework used across the group.
• Build test plans, coverage and regression automation in SystemVerilog, Python and MATLAB.
• Model the analog behavior around the digital design so the loop can be tested before silicon.
• Correlate results across models, RTL simulation, bench and silicon.
• Work with design, firmware and validation engineers to turn requirements into pass/fail criteria.

Skills

SystemVerilog verification

Control theory

DSP concepts

Python for automation

MATLAB

Tools

UVM

AMS

Real Number Modeling

Job description

Senior Staff Digital Engineer in Austin, focused on digital control loop verification, DSP and test automation for advanced power products in AI and high performance computing.

A leading semiconductor company is growing its Austin engineering team. This role owns the verification and test systems that prove digital control loops work as designed, from models through RTL to silicon.

What you'll do

• Verify digital control loops in RTL: stability, frequency response, transient behavior and corner cases
• Turn internal loop analysis tools into a production test framework used across the group
• Build test plans, coverage and regression automation in SystemVerilog, Python and MATLAB
• Model the analog behavior around the digital design so the loop can be tested before silicon
• Correlate results across models, RTL simulation, bench and silicon
• Work with design, firmware and validation engineers to turn requirements into pass/fail criteria

What you'll bring

• Hands on SystemVerilog for digital design verification
• A solid grasp of control loop fundamentals: feedback, Bode plots, phase margin and the effect of delay
• An understanding of sampled systems and DSP: ADCs, sampling, quantization, filtering, latency and metastability
• Python or MATLAB for automation and analysis
• A track record of building verification tools or test frameworks that other engineers adopted

Nice to have

• Mixed signal verification using AMS, DMS or real number modeling
• Power management, DC/DC, PMIC, amplifier, codec or other closed loop experience
• UVM, CDC analysis, behavioral modeling

Package

• Senior Staff level with a strong base and bonus
• Hybrid in Austin, TX
• Relocation and visa sponsorship available
• Strong engineers with around 6 years of experience are in scope, so for many people this is a step up in level