Senior Staff Design Verification Engineer

Renesas Electronics; Austin (TX); On-site; USD 100,000 - 140,000; Full time

Job summary

A leading semiconductor manufacturer located in Austin is seeking a SoC/IP Verification Engineer to join their Infrastructure Power team. In this role, you will architect and maintain verification systems for integrated circuits. Candidates should possess a BS/MSEE and relevant experience, particularly with System Verilog and mixed signal concepts. You will plan verification processes, create verification environments, and work closely with engineering teams to ensure product quality. This position offers the opportunity to contribute to advanced power IC technologies.

Qualifications

• Experience with System Verilog, SVA and functional coverage.
• Deep understanding of event-driven simulator-based modeling techniques.
• Strong problem-solving abilities.

Responsibilities

• Plan the verification of complex SoC & design blocks.
• Create and enhance constrained-random verification environments.
• Debug tests in collaboration with design engineering staff.

Skills

System Verilog

Problem-solving

Communication

Mixed signal concepts

Digital-analog interfaces

Education

BS/MSEE

Tools

Python

Perl

Job description

Renesas is seeking a SoC/IP Verification Engineer for our Infrastructure Power team in Austin, TX, where we develop the most advanced digital power ICs in the industry. We have high caliber talent covering all disciplines of IC development co-located in our Austin design center. You will work alongside the full spectrum of contributors to your products, including marketing, applications, logic design, analog design, firmware, verification, validation, software, product, and test engineers.

You will architect, design, and maintain verification systems for integrated circuits that supply power to the largest and most powerful advanced computing platforms. Your contributions will span low level circuits to large system design, and you will see those systems all the way through to high volume manufacturing.

In this role, you will use your design and verification expertise to verify complex power management IC designs collaborating closely with design and verification engineers in active projects and perform hands-on verification. Using your System Verilog coding and problem-solving skills, you will build efficient and effective constrained-random verification environments that exercise designs through typical and corner-cases to uncover design errors. You will be responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage

Job Description

• Plan the verification of complex SoC & design blocks by fully understanding the design specification
• Interact with design/system engineers to identify important verification scenarios
• Create and enhance constrained-random verification environments using System Verilog.
• Create and support UVM compliant test-bench architecture
• Formally verify designs with SVA and industry leading formal tools
• Identify and write various coverage metrics for stimulus and corner-cases
• Build reusable DV infrastructure components for both block and top-level environments
• Debug tests in collaboration with design engineering staff
• Build verification tools for system automation, regressions, and reporting

Qualifications

• BS/MSEE & relevant work experience
• Experience with System Verilog, SVA and functional coverage
• Deep understanding of event-driven simulator-based modeling techniques
• Advance knowledge of mixed signal concepts and digital-analog interfaces
• Developed and executed several comprehensive SoC and block level verification plans
• Worked on commercially successful IC’s
• Strong problem-solving abilities
• Clear written and verbal communications, including code documentation
• Preferred:
• 5-12 years of relevant experience in the design and/or verification of mixed signal and digital IC’s
• Experience in the verification of power management ICs, high speed interfaces, or peripheral controllers
• Strong knowledge of VIP integration of High-speed interface protocols
• Experience in SVRNM modelling and verification
• Prior experience in the development of verification strategy, test design, and test infrastructure
• Proficiency with a scripting language like Python/Perl
• Familiarity with FPGA emulation techniques
• Understanding of firmware (C language) based test routines to run on embedded MC