Staff / Senior Staff Physical Design Engineer

Bolt Graphics; Sunnyvale (CA); On-site; USD 200,000 - 220,000; Full time

Benefits offered by this job

Medical, Dental & Vision premiums 100%

Equity - Stock Options

401(k) match

Job summary

Bolt Graphics in Sunnyvale, CA, is seeking a Staff / Senior Staff Physical Design Engineer to drive full-chip physical implementation from netlist to GDSII, targeting timing, power, and area targets for high-performance graphics processors.

This on-site role requires 5 days in the office, with ownership of flow, timing closure, signoff, and cross-functional collaboration with RTL, architecture, and foundry teams.

Qualifications

• Bachelor's/Master's degree in Electrical Engineering or related field.
• 8-12 years of ASIC physical design experience.
• Proven experience in full-chip or large block implementation and tapeouts.
• Strong expertise in floorplanning and power planning.
• Placement, CTS, routing, and physical verification.
• Static Timing Analysis (STA) and timing closure.
• Hands-on with industry-standard tools such as Synopsys ICC2 and Cadence Innovus.
• Experience with advanced nodes (7nm and below preferred).
• Strong debugging and problem-solving skills.

Responsibilities

• Own end-to-end physical design flow: synthesis support, floorplanning, placement, CTS, routing, signoff.
• Drive timing closure across multiple PVT corners using STA methodologies.
• Perform and debug DRC/LVS/EM/IR issues and drive clean signoff.
• Collaborate with RTL, architecture, and verification teams for design convergence.
• Handle ECO flows, including late-stage timing and functional fixes.
• Optimize designs for power, performance, and area (PPA).
• Integrate and validate hard macros (SRAMs, IOs, analog blocks).
• Develop automation scripts (TCL/Python) for PD flows.
• Collaborate with foundry/vendor teams during tapeout and signoff.

Skills

Floorplanning

Power planning

Placement

CTS

Routing

SDA/STA

Signoff

Python/TCL scripting

Debugging

Education

Bachelor's/Master's in Electrical Engineering

Tools

Synopsys ICC2

Cadence Innovus

Advanced node knowledge (7nm)

Job description

Staff / Senior Staff Physical Design Engineer

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

Our Values

• Be Fearless: Unmute yourself. Test boundaries and get proven right.
• Remain Adaptable: Stay comfortable in a continuously changing world. If you're wrong, concede and move on.
• Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role:

As a Staff / Senior Staff Physical Design Engineer , you will be responsible for driving full-chip or block-level physical implementation from netlist to GDSII. You will play a critical role in achieving timing, power, and area (PPA) targets while ensuring high-quality tapeouts. This is an on-site role and will require presence in the office 5 days a week . No hybrid option is available.

What you'll do:

• Ownend-to-end physical design flow: synthesis support, floorplanning, placement, CTS, routing, and signoff
• Drivetiming closure(setup/hold) across multiple PVT corners using advanced STA methodologies (OCV/POCV)
• Perform and debugDRC/LVS/EM/IRissues and drive clean signoff
• Work closely with RTL, architecture, and verification teams fordesign convergence
• HandleECO flows, including late-stage timing and functional fixes
• Optimize designs forpower, performance, and area (PPA)
• Integrate and validatehard macros (SRAMs, IOs, analog blocks)
• SupportGLS, SDF generation, and debug timing-related issues
• Develop and enhanceautomation scripts(TCL/Python) for PD flows
• Collaborate with foundry/vendor teams duringtapeout and signoff

Required Qualifications:

• Bachelor's/Master's degree in Electrical Engineering or related field
• 8-12 years of experiencein ASIC physical design
• Proven experience infull-chip or large block implementation and tapeouts
• Strong expertise in:
• Floorplanning and power planning
• Placement, CTS, routing, and physical verification
• Static Timing Analysis (STA) and timing closure
• Hands-on experience with industry-standard tools such as:
• Synopsys ICC2/Cadence Innovus
• Experience with advanced nodes (7nm and below preferred)
• Strong debugging and problem-solving skills

Preferred Qualifications:

• Experience withlow-power design techniques (UPF/CPF)
• Knowledge ofEMIR analysis(e.g.,Ansys RedHawk-SC)
• Familiarity withmulti-voltage designs and power domains
• Experience withhigh-speed interfaces or complex SoCs (CPU/GPU/AI)
• Exposure toGLS and timing-related silicon debug
• Scripting expertise inPython/TCL

Compensation Range: $200,000-220,000 per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.

• Medical, Dental, & Vision - 100% covered premiums
• Equity - Stock Options
• 401(k) match

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.