Senior STA Engineer – Timing & Power Convergence

Efficient Computer Company; Pennsylvania; Hybrid; USD 180.000 - 260.000; Vollzeit

Benefits dieser Stelle

Annual bonus

Equity

Benefits

401(k) match

Paid parental leave

Zusammenfassung

Efficient Computer is seeking a Physical Design Engineer - Timing Lead to join our growing hardware team. The role focuses on timing convergence for our energy-efficient general-purpose processor in advanced nodes and requires close collaboration with RTL, DFT, and IP vendors.

You will drive timing flows, sign-off readiness, and timing margining across IP, Subsystem, and SOC blocks, while helping shape the future of low-power, high-performance computing.

Qualifikationen

• Master's degree in Electrical Engineering with 5+ years of industry experience, or PhD in Electrical Engineering with 3+ years.
• Proven track record of delivering STA sign-off for multiple tape-outs in 12nm or below process technologies.
• Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques

Aufgaben

• Develop timing flows and methodologies for finfet and multi-patterning–based technologies from scratch in Cadence Tempus or Synopsys Primetime.
• Own and drive timing convergence of IP, Subsystem and SOC blocks.
• Define timing margining, PVTRC corner definitions, extraction methodology, signoff timing to SYN/PNR correlation.
• Develop slew rate, glitch noise checks to ensure robust design quality.
• Develop custom timing checks for Efficient's Ultra low power architecture.
• Work with RTL, DFT and IP vendors to define and drive SDC constraints.
• Coordinate with post-Si bring-up teams to ensure pre-Si to post-Si timing correlation.
• Collaborate with 3rd party vendor resources in timing domain.
• Improve flow consistency and efficiency across multiple product lanes

Kenntnisse

Timing convergence

STA sign-off

Scripting: TCL/Python/Shell

Low power design

High-frequency design

Ausbildung

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence

Synopsys

Mentor

Hspice

Jobbeschreibung

Efficient Computer is seeking a Physical Design Engineer - Timing Lead to join our growing hardware team. The role focuses on timing convergence for our energy-efficient general-purpose processor in advanced nodes and requires close collaboration with RTL, DFT, and IP vendors.

You will drive timing flows, sign-off readiness, and timing margining across IP, Subsystem, and SOC blocks, while helping shape the future of low-power, high-performance computing.