Senior STA Engineer for Cloud-Scale ASIC Timing

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 213,000 - 288,000; Full time

Job summary

AWS UC seeks a Senior Physical Design STA Engineer in Cupertino, CA to lead block and full-chip timing analysis for cloud server platforms. You’ll craft timing constraints, run STA flows, and guide ECOs and sign-off activities across RTL-to-GDSII processes.

You’ll work with RT/Arch and PD teams to optimize performance, cost, and reliability in a fast-paced data-center environment, contributing to AWS Inferentia and related hardware initiatives.

Qualifications

• BS + 8yrs or MS + 6yrs or PhD + 4yr in EE/CS
• Experience in scripting languages (Python, Ruby, Perl)
• Expertise in timing analysis fundamentals
• 3+ years doing Static Timing Analysis
• 3+ years with timing constraint development
• Timing Analysis using EDA tools (PrimeTime, Tempus, or others)
• Understanding of ASIC Physical Design from RTL-to-GDSII
• Understanding of other sign-off activities (ir/em, physical verification, DFT)

Responsibilities

• Develop & maintain flows for block and full-chip level static timing analysis
• Write, debug & validate timing constraints for blocks and full-chip.
• Run Static Timing Analysis and give frequent feedback to team members and leads.
• Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues).
• Develop scripts to automate running timing analysis and generate reports.
• Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams

Skills

Scripting (Python/Ruby/Perl)

STA fundamentals

Static Timing Analysis

Constraint development

STA tools (PrimeTime/Tempus)

ASIC physical design RTL-to-GDSII

Sign-off activities (em/physical/DFT)

Education

BS + 8yrs or MS + 6yrs or PhD + 4yr in EE/CS

Tools

PrimeTime

Tempus

STAR-RC/Quantus

SPICE/SPECTRE

Job description

AWS UC seeks a Senior Physical Design STA Engineer in Cupertino, CA to lead block and full-chip timing analysis for cloud server platforms. You’ll craft timing constraints, run STA flows, and guide ECOs and sign-off activities across RTL-to-GDSII processes.

You’ll work with RT/Arch and PD teams to optimize performance, cost, and reliability in a fast-paced data-center environment, contributing to AWS Inferentia and related hardware initiatives.