SRAM Circuit Design Engineer - Memory IP Innovator

Longwood University; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Job summary

NVIDIA in Santa Clara, CA, is seeking an SRAM circuit designer to join the Digital IP group. You will work on transistor-level SRAM design, supervise layout, verify SRAM macros, and help bring IP into production.

The role also includes SRAM compiler development, exploring future process nodes, and guiding SOC design and silicon test to meet demanding application needs at scale, with equity and benefits.

Qualifications

• Master's degree or higher in Electrical Engineering or related field (or equivalent experience).
• SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET and nanosheet processes.
• Design experience in single-port, dual-port, or register file SRAM-based macros, including complex circuits such as self-timed logic and sense-amplifiers.
• Familiarity with Cadence Virtuoso schematic and layout capture tools.
• Shown delivery of silicon IP into production.

Responsibilities

• Embedded SRAM design: transistor-level circuit design, supervising layout, and verification of SRAM macros.
• SRAM compiler development: automate assembly/validation of SRAM macros using NVIDIA compute resources.
• Advanced development: explore future nodes and optimize power, performance, and area.
• Guide SOC design, silicon test, and productization with partners.

Skills

SRAM design

Digital circuit design

Layout & validation

Cadence Virtuoso

Silicon IP delivery

Codex

Claude Code

Education

Master's degree in Electrical Engineering or related field

Tools

Cadence Virtuoso

Job description

NVIDIA in Santa Clara, CA, is seeking an SRAM circuit designer to join the Digital IP group. You will work on transistor-level SRAM design, supervise layout, verify SRAM macros, and help bring IP into production.

The role also includes SRAM compiler development, exploring future process nodes, and guiding SOC design and silicon test to meet demanding application needs at scale, with equity and benefits.