Design Engineer

EDA CAREERS, (Technology Futures Inc).; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Performance bonus

Equity

Job summary

EDA CAREERS, (Technology Futures Inc.) seeks a Senior SRAM Memory Circuit Design Engineer (Architect) to lead 3D SRAM development in Silicon Valley, with remote possibilities for highly skilled designers.

You will define memory array architectures, design peripheral circuits, and own tests and validation from concept through tapeout, collaborating with architecture, device, and packaging teams.

Qualifications

• Experience in SRAM memory circuit design and array architectures.
• Define memory array architecture, organization, and read/write/standby schemes for thyristor-based cells.
• Design peripheral circuits including sense amplifiers, write drivers, wordline/bitline drivers, decoders, timing control, and power management.
• Design for test (DFT/BIST), redundancy and repair, and ECC strategies; support RTL for silicon bring-up.

Responsibilities

• Architect memory circuits for 3D SRAM from array to product macros.
• Lead design and verification across process, voltage, and temperature corners.

Skills

Simulation

Layout review

Test Chips

Memory design

DFT/BIST

ECC strategies

3D SRAM

Job description

Senior SRAM Memory Circuit Design Engineer(s) (Architect)

From Senior Engineers, Management, Director #8444

Silicon Valley preferred (Remote may be possible for VERY skilled and experienced memory designers)

ABOUT:

My client is a thriving start-up developing custom 3D SRAM and advanced packaging. Their highly skilled management team has led the way in memory design and AI growth. They have a few critical openings for Founding Engineers at senior levels. Applicants must be highly skilled in Memory Design. Get in on the ground floor as they ramp up with their cutting-edge memory technology.

Their mission is to break the “memory wall”—the bottleneck that limits how fast frontier AI can grow. With 80 granted patents, backed by $37M in funding and support from leading hyper-scalars, they are building its team from the ground up.

Your contribution:

As a Senior Memory Circuit Design Engineer to architect, you will design the circuits that bring their 3D SRAM to life—from array architecture and peripheral circuits to test chips and product macros.

To be considered, you should have experience (at various levels) in SRAM Memory Circuit Design and Array Architectures. You will define memory array architecture, organization, and read, write, and standby schemes for their thyristor-based cell, Design peripheral circuits, including sense amplifiers, write drivers, wordline and bitline drivers, decoders, timing control, and power management and Design for the cell’s operating windows, disturb limits, and variability, working from the cell electrical design rules

SKILLS:

• Simulation, Verification & Layout...you will Run circuit simulation across process, voltage, and temperature corners, including Monte Carlo analysis for margins and yield.
• Drive design verification, parasitic extraction, and post-layout analysis for multi-layer 3D arrays and guide and review custom layout with layout engineers
• Test Chips & Silicon Validation...Design memory test chips and product macros, from schematic through tapeout; Define design-for-test (DFT/BIST), redundancy and repair, and ECC strategies; Support RTL team for silicon bring-up, bitmap analysis, and debug, and feed silicon results back into the next design
• Characterize memory behavior of AI training and inference workloads, including bandwidth, access patterns, capacity, and data reuse
• Build and maintain analytical and simulation models of AI accelerator and memory subsystems
• Partner with architecture, circuit design, and device teams to translate performance targets into design requirements
• Work with device and process engineers on sense margins, read and write schemes, and cell and array trade-offs
• Work with packaging engineers on the interface between the memory and compute logic in 3D and hybrid-bonded stacks
• Memory Design You make sound trade-offs across density, speed, power, margin, and yield, and you design for real silicon variability.
• Hands-On Ownership You take designs from concept through tapeout and silicon debug, and you stay with a problem until it’s solved.

COMPENSATION & BENEFITS

• Base salary: top 30%-tile salary for SF Bay Area - Performance bonus -Equity