Senior Software Architect

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 210,000 - 390,000; Full time

Benefits offered by this job

401(k) match

Employee stock purchase plan

Medical, dental, and vision plans

Job summary

Cadence Design Systems, Inc. in San Jose seeks a Senior Engineer for the System Verification Group to advance the Xcelium RTL/logic simulator and tackle the next generation of AI and hyperscale chip designs.

You will design, optimize, and lead others in C++ development, RTL/Verilog knowledge, and SDC constraint handling, with a collaborative global team and a strong emphasis on performance.

Qualifications

• MS in Computer Science or Electrical Engineering with extensive experience (12+ years) or PhD with 10+ years.
• 10+ years in EDA software development.
• Strong RTL/Logic Simulation, SDC constraints, and Timing Analysis knowledge.
• Excellent C/C++ programming and familiarity with SystemVerilog/Verilog.
• Experience with multi-threaded/concurrent programming.
• Ability to learn new technologies quickly and adapt to project requirements.

Responsibilities

• Enhance and support Xcelium RTL/logic simulator engine with new features.
• Enhance Timing Constraints Verification technology in Xcelium.
• Design and optimize graph algorithms for multi-billion-node graphs with SDC support.
• Perform deep-dive bottleneck analysis and optimize performance in C/C++.

Skills

C++

SystemVerilog/Verilog

RTL/Logic Simulation

SDC constraints

Multi-threaded programming

Leadership

Education

MS in Computer Science or Electrical Engineering

PhD in Computer Science or Electrical Engineering

Tools

Verilog/SystemVerilog tooling

SDC tooling

Job description

SAN JOSE

Full time

R56465

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning.

We are looking for experienced C++ software engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.

Responsibilities:

• Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.

• Enhance and support Timing Constraints Verification technology used inside Xcelium simulator.

• The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi‑billion‑node graphs.

• Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.

• Lead junior engineers and collaborate with global team members to deliver high-quality results in a distributed environment.

• Contribute to technical discussions, code reviews, and process improvements.

• Write Specifications and Unit Tests for your code.

Position Requirements/Qualifications:

• MS in Computer Science or Electrical Engineering with a minimum of 12 years of experience OR PhD with a minimum of 10 years of experience

• 10+ years of experience in EDA software development.

• Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool.

• Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog.

• Experience in multi-threaded/ concurrent programming.

• Ability to quickly learn new technologies and adapt to project requirements.

• Prior experience with RTL/logic simulation software development is an added plus.

The annual salary range for California is $210,000 to $390,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.