Senior SoC Verification Engineer: Digital and Power

Renesas; Austin (TX); On-site; USD 130,000 - 180,000; Full time

Job summary

Renesas is seeking a Senior Digital Design Verification Engineer to join our team developing complex power management SoCs. You will own verification of significant blocks and features from planning through closure, using SystemVerilog/UVM, coverage-driven verification, and advanced debugging.

You will collaborate with architecture, RTL design, firmware, analog, validation, and systems teams to ensure robust regression and automation.

Qualifications

• Bachelor's or Master’s degree in Electrical/Computer Engineering, CS or related field.
• 4+ years of digital design verification experience or equivalent.
• Ownership of a complex block/feature from planning to closure.
• Strong SystemVerilog, UVM, constrained random, coverage, and SV assertions knowledge.

Responsibilities

• Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.
• Develop feature-based verification plans from product and architectural specs; identify gaps and risks.
• Build reusable SystemVerilog/UVM environments with sequences, monitors, scoreboards, checkers, assertions, and coverage models.
• Develop constrained random and targeted tests for normal operation, error handling, and system-level interactions.
• Drive functional, code, toggle, FSM, and coverage closure using regression and coverage data.
• Debug RTL, testbench, assertion, integration, and regression failures with cross-team collaboration.
• Automate regression, triage, reporting, and analysis workflows using scripting tools.
• Communicate status, risks, dependencies, and closure evidence clearly; guide less-experienced engineers.

Skills

SystemVerilog

UVM

Constrained random

Coverage-driven verification

SystemVerilog Assertions

RTL verification

Debug skills

Python

Linux scripting

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Cadence Xcelium

SimVision

vManager

JasperGold

Synopsys VCS

Verdi

Job description

Renesas is seeking a Senior Digital Design Verification Engineer to join our team developing complex power management SoCs. You will own verification of significant blocks and features from planning through closure, using SystemVerilog/UVM, coverage-driven verification, and advanced debugging.

You will collaborate with architecture, RTL design, firmware, analog, validation, and systems teams to ensure robust regression and automation.