Senior Digital Verification Engineer – Power-Management SoCs

Renesas Electronics Corporation; Austin, Northern (TX, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Renesas Electronics Corporation is seeking a Senior Digital Design Verification Engineer in Austin to own and drive verification of key digital blocks within power management SoCs. You will build reusable UVM environments, develop test plans, and coordinate across architecture, RTL, firmware, and validation teams.

The role emphasizes coverage closure, constrained random testing, and thorough debugging of RTL/testbench issues, with opportunities to influence verification methodology and

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4+ years of relevant digital design verification experience.
• Demonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure.
• Strong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions.
• Experience translating specifications into test plans, test scenarios, checkers, scoreboards, assertions, coverage models, and closure criteria.
• Hands-on experience developing and debugging reusable UVM environments and analyzing complex regression failures.
• Strong RTL and testbench debug skills, with the ability to distinguish design, environment, test, firmware, and specification issues.

Responsibilities

• Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.
• Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks.
• Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models.
• Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions.
• Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data.
• Debug RTL, testbench, assertion, integration, and regression failures; collaborate with design and firmware teams to isolate issues and verify fixes.
• Automate regression, triage, reporting, and analysis workflows using scripting and modern engineering tools.
• Communicate status, risks, dependencies, and closure evidence clearly; provide technical guidance to less-experienced engineers.

Skills

SystemVerilog

UVM

Constrained random verification

Functional coverage

SystemVerilog Assertions

Education

Electrical, Computer Engineering, Computer Science or related field

Tools

Cadence Xcelium

SimVision

vManager

JasperGold

Synopsys VCS

Verdi

Job description

Renesas Electronics Corporation is seeking a Senior Digital Design Verification Engineer in Austin to own and drive verification of key digital blocks within power management SoCs. You will build reusable UVM environments, develop test plans, and coordinate across architecture, RTL, firmware, and validation teams.

The role emphasizes coverage closure, constrained random testing, and thorough debugging of RTL/testbench issues, with opportunities to influence verification methodology and