Senior Digital Verification Engineer – DDR6, Onsite

Renesas Electronics; Duluth (GA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical insurance

Health Savings Account

Dental insurance

Vision insurance

Life insurance

AD&D

Pet insurance

Paid time off

Job summary

Renesas Electronics seeks a senior memory interface verification engineer to lead the verification of DDR5/DDR6 data buffer blocks for high-bandwidth datacenter and AI/cloud applications. You will drive verification strategy, test plans, coverage, and reusable UVM-based testbenches.

The role requires extensive SystemVerilog/UVM expertise, collaboration with design and software teams, and ownership of verification environments for assigned blocks in a fast-paced semiconductor setting.

Qualifications

• Masters in Electrical Engineering, Computer Engineering, or equivalent with 7+ years of experience.
• Bachelor's Degree in Electrical Engineering, Computer Engineering, or equivalent with 9+ years of experience.

Responsibilities

• Drive memory interface product verification strategy and test plans.
• Develop and maintain verification environments and test benches using UVM.
• Coordinate with design team to ensure testability and requirements coverage.
• Lead verification planning, coverage analysis, and checker development.

Skills

UVM verification

SystemVerilog

DDR memory interfaces

Testbench development

Verification planning

Debugging

Education

Master's in Electrical Engineering or Computer Engineering

Bachelor's in Electrical Engineering or Computer Engineering

Tools

UVM

Verilog/SystemVerilog

Job description

Renesas Electronics seeks a senior memory interface verification engineer to lead the verification of DDR5/DDR6 data buffer blocks for high-bandwidth datacenter and AI/cloud applications. You will drive verification strategy, test plans, coverage, and reusable UVM-based testbenches.

The role requires extensive SystemVerilog/UVM expertise, collaboration with design and software teams, and ownership of verification environments for assigned blocks in a fast-paced semiconductor setting.