Senior SoC Verification Engineer — Multi-Chip & SMC

AI Chopping Block; Santa Clara, Northern (CA, KY); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller (SMC) and enable scalable multi-die integration. You will design and run tests, build DV infrastructure, and debug flows across chiplet-based SoCs.

You’ll collaborate with distributed teams, mentor remotely, and apply SystemVerilog, SV-UVM, Python, and C/C++ to verify advanced hardware/software interfaces in a fast-paced AI platform environment.

Qualifications

• Proficient in SystemVerilog with SV-UVM experience.
• Experience writing test plans and DV infrastructure.
• Comfortable working with remote mentorship and distributed teams.

Responsibilities

• Develop and maintain SMC tests and supporting DV infrastructure.
• Write, execute, and track test plans for chiplet and multi-chip SoC designs.
• Use C/C++ to develop tests compiled, loaded, and executed directly on the DUT.
• Triage, analyze, and debug issues in collaboration with design/architecture teams.

Skills

SystemVerilog

SV-UVM

Python

C/C++

Tools

Cocotb

Job description

Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller (SMC) and enable scalable multi-die integration. You will design and run tests, build DV infrastructure, and debug flows across chiplet-based SoCs.

You’ll collaborate with distributed teams, mentor remotely, and apply SystemVerilog, SV-UVM, Python, and C/C++ to verify advanced hardware/software interfaces in a fast-paced AI platform environment.