Senior SoC RTL Engineer - Drive Timing to Silicon

Synopsys Inc; Sunnyvale (CA); On-site; USD 130,000 - 180,000; Full time

Job summary

Synopsys Inc is seeking an experienced RTL designer to contribute to block-level designs in Verilog/SystemVerilog/VHDL for SoC subsystems. You will ensure clean handoff with RTL quality checks and collaborate with verification and physical design teams to meet timing and area targets.

The role emphasizes implementing industry-standard protocols and using scripting to automate recurring design tasks across global teams, enabling efficient silicon delivery.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 3–4 years hands-on ASIC/FPGA RTL design, implementation and debug.
• Proficiency in Verilog, SystemVerilog, or VHDL RTL coding for registers, pipelines, state machines, memories and FIFOs.
• Understanding of ASIC design flow from micro-architecture through RTL development, synthesis and timing closure.
• Experience with industry-standard tools: simulators, lint checkers, CDC/RDC analysis tools, synthesis tools, and static timing analysis.
• Experience with interface protocols: AXI, APB, AHB, I2C and SPI.

Responsibilities

• Write and review Verilog, SystemVerilog, or VHDL RTL for block-level designs based on micro-architecture specifications.
• Run RTL quality checks using linting, CDC/RDC analysis, and synthesis to ensure clean handoff to physical design.
• Collaborate with verification engineers to debug testbench failures and close coverage gaps.
• Work with physical design teams to resolve timing issues and support timing closure from netlist through signoff.
• Implement standard interface protocols (AXI, APB, AHB, I2C, SPI) within SoC subsystems.
• Use Python, Tcl, or shell scripting to automate tasks in the design flow.

Skills

Verilog

SystemVerilog

VHDL

ASIC/FPGA RTL design

Timing closure

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Simulators

Lint checkers

CDC/RDC analysis tools

Synthesis tools

Static timing analysis

Job description

Synopsys Inc is seeking an experienced RTL designer to contribute to block-level designs in Verilog/SystemVerilog/VHDL for SoC subsystems. You will ensure clean handoff with RTL quality checks and collaborate with verification and physical design teams to meet timing and area targets.

The role emphasizes implementing industry-standard protocols and using scripting to automate recurring design tasks across global teams, enabling efficient silicon delivery.