Senior SoC RTL Design Architect

Nutanix; Santa Clara (CA); On-site; USD 147,000 - 190,000; Full time

Job summary

Qualcomm Atheros, Inc. seeks an engineer to independently plan and execute digital architecture and RTL coding for next‑generation wireless and wired ASICs. You will verify and deliver complex ASICs, work on RF/debug tasks, and support cross‑functional teams in SoC integration.

The role involves testing platforms, performance optimization, and collaboration with hardware and software groups across mobile and consumer electronics markets.

Qualifications

• Moderately-defined responsibility for digital architecture and design, Verilog RTL coding, implementation and verification of next generation wireless and wired ASICs.
• Test and debug of test platform hardware and digital circuit component level and RF debugging.
• Work with cross-functional teams to plan and execute verification and validation subsystems for SoCs.

Responsibilities

• Plan, perform and verify digital architecture and RTL design of ASICs.
• Support design engineers with tests and data reporting.
• Collaborate on high speed digital and mixed-signal board design and integration into SoCs.

Job description

Qualcomm Atheros, Inc. seeks an engineer to independently plan and execute digital architecture and RTL coding for next‑generation wireless and wired ASICs. You will verify and deliver complex ASICs, work on RF/debug tasks, and support cross‑functional teams in SoC integration.

The role involves testing platforms, performance optimization, and collaboration with hardware and software groups across mobile and consumer electronics markets.