ASIC Verification Engineer - RTL & Synthesis Focus

Qualcomm; Santa Clara, Northern (CA, KY); Hybrid; USD 113,000 - 170,000; Full time

Job summary

Qualcomm Atheros, Inc. is seeking candidates for roles focusing on implementing optimal system architectures and logics for connectivity RF/Analog systems. You will participate in developing leading-edge ASICs for multi-function mobile platforms and assist with synthesis, gate-level simulation, and timing of the chip.

The ideal candidate should have RTL Design experience, ASIC front-end exposure, and scripting knowledge in Perl or Python to help drive efficient verification and implementation.

Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• RTL Design experience required.
• Scripting languages such as Perl or Python preferred.

Responsibilities

• Develop optimum system architectures, interfaces and logics for connectivity RF/Analog systems.
• Participate in the development of leading-edge ASICs for multi-function mobile platforms.
• Assist in synthesis, gate-level simulation and timing of the chip.

Skills

RTL Design

ASIC front-end

Scripting (Perl/Python)

Education

Bachelor's degree in Science/Engineering

Job description

Qualcomm Atheros, Inc. is seeking candidates for roles focusing on implementing optimal system architectures and logics for connectivity RF/Analog systems. You will participate in developing leading-edge ASICs for multi-function mobile platforms and assist with synthesis, gate-level simulation, and timing of the chip.

The ideal candidate should have RTL Design experience, ASIC front-end exposure, and scripting knowledge in Perl or Python to help drive efficient verification and implementation.