Power & Limits Architect for High-Performance SoCs

MaC VC; San Diego (CA); On-site; USD 174,000 - 262,000; Full time

Benefits offered by this job

RSU grants

Annual bonus

Job summary

Qualcomm Technologies, Inc. in San Diego, CA, is seeking an experienced ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP for high-performance, low-power products.

You will collaborate with cross-functional groups to determine product execution path. The role requires 10+ years in power and limits systems, strong UPF and power-domain crossing skills, low power design experience, and scripting in Perl/Python.

Qualifications

• Bachelors/Masters/PhD with ASIC design/verification experience.
• Experience with power/limits architectures and IPC concepts.
• Experience in low power methodologies and timing considerations.

Responsibilities

• Define, model, design, and optimize IP/SoC for high-performance products.
• Verify, validate, and document ASIC power and limits systems.
• Collaborate with cross-functional teams to determine execution paths.
• Ensure thermal and electrical limits are met with minimal SW intervention.

Skills

Power and limits design

UPF & power domain crossing

Low power design

Scripting: Perl/Python

Post-Si debug

Education

Bachelor's degree in Science/Engineering or related field

Master's degree in Science/Engineering or related field

PhD in Science/Engineering or related field

Job description

Qualcomm Technologies, Inc. in San Diego, CA, is seeking an experienced ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP for high-performance, low-power products.

You will collaborate with cross-functional groups to determine product execution path. The role requires 10+ years in power and limits systems, strong UPF and power-domain crossing skills, low power design experience, and scripting in Perl/Python.