Senior Layout Design Engineer – Top‑Level Chip Planning Lead

SiTime Corporation; United States; Remote; USD 150.000 - 190.000; Vollzeit

Benefits dieser Stelle

Quarterly bonus

Equity grants

Zusammenfassung

SiTime Corporation is seeking a Sr. Layout Design Engineer to lead top-level chip-planning and perform comprehensive CMOS/BiCMOS layout work.

You will coordinate with offshore teams, mentor junior engineers, and help develop standard layout methodologies across sites, contributing to build processes and achieving high layout quality. The role involves remote interfacing with global teams, floor planning, layout verification (DRC/LVS/ERC), and chip-level integration.

Qualifikationen

• BA/BS degree in layout design or related field.
• 10 years’ experience with layout design for analog and full-custom digital blocks.

Aufgaben

• Lead top-level chip-planning and perform block-level and top-level layouts for CMOS and BiCMOS circuits.
• Review and coordinate work content with offshore layout teams across time zones.
• Train junior layout engineers and offshore contractors; develop common best practices across sites.

Ausbildung

BA/BS Degree in Layout Design or related field

Tools

Cadence Virtuoso

Cadence PVS

Mentor Calibre

Jobbeschreibung

SiTime Corporation is seeking a Sr. Layout Design Engineer to lead top-level chip-planning and perform comprehensive CMOS/BiCMOS layout work.

You will coordinate with offshore teams, mentor junior engineers, and help develop standard layout methodologies across sites, contributing to build processes and achieving high layout quality. The role involves remote interfacing with global teams, floor planning, layout verification (DRC/LVS/ERC), and chip-level integration.