DFT Test Engineer: RTL & ATPG

Apple Inc.; Cupertino (CA); Hybrid; USD 147,000 - 218,000; Full time

Benefits offered by this job

Stock-based compensation programs

Education reimbursement

Medical and dental coverage

Retirement benefits

Employee stock purchase plan

Excellent relocation support

Job summary

Apple Inc. in Cupertino, CA is seeking a DFT/RTL engineer to design and implement DFT architectures for complex chips. The role collaborates with design and verification teams, runs STA checks, and develops ATPG test vectors to improve yield.

You will engage with test engineers to bring up vectors on silicon and work on power reduction strategies. Qualifications include a Master’s in a related field and strong Verilog, DFT, ATPG, and scripting experience.

Qualifications

• Master’s degree in Computer Engineering, Electrical Engineering, Electronics Engineering, or related field with 2 years of related experience.
• Experience designing and verifying RTL using Verilog.
• Knowledge of MBIST, march algorithms and memory fault models.
• Experience designing JTAG architecture and DFT control registers.
• Automation of DFT design flows using Python or Perl.
• Knowledge of STA for timing analysis and RTL/gate-level simulations.

Responsibilities

• Develop and document DFT architecture and specifications.
• Implement DFT infrastructure and RTL Verilog for DFT logic.
• Collaborate with designers to integrate DFT and run checks.
• Coordinate with DV team to verify RTL and gate-level designs.
• Generate ATPG vectors and analyze test coverage across fault models.
• Engage with test engineers to bring up vectors on silicon.
• Support TTR and silicon diagnosis efforts.
• Handle schedules and multi-functional engineering tasks.
• Apply low-power techniques to reduce chip power consumption.

Skills

RTL design & verification

Verilog

Python/Perl scripting

JTAG/DFT control

STA timing analysis

ATPG & test vectors

Silicon failure analysis

Low-power design

Education

Master’s degree in Computer/Electrical/Electronics Engineering

Tools

VCS

NCSIM

Job description

Apple Inc. in Cupertino, CA is seeking a DFT/RTL engineer to design and implement DFT architectures for complex chips. The role collaborates with design and verification teams, runs STA checks, and develops ATPG test vectors to improve yield.

You will engage with test engineers to bring up vectors on silicon and work on power reduction strategies. Qualifications include a Master’s in a related field and strong Verilog, DFT, ATPG, and scripting experience.