Senior SOC Design & Integration Engineer

AMD; Boxborough (MA); On-site; USD 140,000 - 190,000; Full time

Job summary

AMD's SOC design team is seeking a self-driven engineer to own design and integration efforts from RTL to full-chip construction, shaping latency, performance, and IP integration. You will collaborate with IP development, verification, front-end integration, and physical design teams to deliver advanced silicon and drive critical design decisions across the stack.

The ideal candidate has strong Verilog RTL experience, knowledge of AXI/PCIe buses, timing analysis, and proactive communication to

Qualifications

• BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE.
• Verilog RTL development in CPU/SOC/ASIC environment is required.
• Experience with SOC design and RTL development is preferred.

Responsibilities

• Drive SOC-level design and integration.
• Integrate IP, SOC fabric, voltage and clock crossings, clocks, resets, fuses and I/O.
• Develop RTL design and coding for SOC sections and related logic.
• Own SOC power design.
• Perform static verification of RTL, CDC, Power and Connectivity.
• Lead one of the defined design domains.

Skills

Verilog RTL development

SOC integration

System bus protocols

Power implementation UPF

Static timing analysis

Cross-functional collaboration

Formal verification

Scripting skills

Education

BE/B.Tech/ME/M.Tech in ECE/EEE

SOC design and Verilog RTL development preferred

Job description

AMD's SOC design team is seeking a self-driven engineer to own design and integration efforts from RTL to full-chip construction, shaping latency, performance, and IP integration. You will collaborate with IP development, verification, front-end integration, and physical design teams to deliver advanced silicon and drive critical design decisions across the stack.

The ideal candidate has strong Verilog RTL experience, knowledge of AXI/PCIe buses, timing analysis, and proactive communication to