Principal SoC Design Engineer / SoC Lead

Neurophos, Inc.

Austin, Northern (TX, KY)

Hybrid

USD 180,000 - 240,000

Full time

14 days+
Application generator

An application made for this job — a tailored resume and cover letter that speak straight to the posting.

Get past ATS filters

Benefits offered by this job

Health insurance
HSA contributions
Unlimited PTO
401(k) matching
Stock options
Voluntary benefits
Personalized benefits

Job summary

Neurophos is seeking an SoC Lead to own the integration of the full chip or major module for a bandwidth-challenging system. You will determine top-level integration flows and collaborate with system architects, RTL, physical design, and verification leads to optimize tradeoffs.

In this breadth role, you’ll mentor engineers, scale the design organization, and contribute to tapeout readiness while staying hands-on across multiple domains.

Qualifications

  • Principal-level technical leadership with multiple full-chip tapeouts.
  • Breadth across domains: system, timing, interconnect architecture.
  • Deep experience in CPU design or high-speed interconnect/data-fabric design.
  • Experience with advanced process nodes and high-bandwidth I/O.

Responsibilities

  • Lead integration of the full chip or major module, owning top-level integration flows.
  • Make and own cross-domain technical decisions spanning system functionality, DFT, power, timing, and interconnect/data-fabric architecture.
  • Partner across microarchitecture, RTL, physical design, verification, and DFT to resolve system-level tradeoffs.
  • Go deep on any domain when needed, staying hands-on with the flow at every level.
  • Help scale the design org: hire, mentor, and grow engineers across specialty domains.
  • Represent chip-level architecture in the context of advanced-node, high-speed, high-bandwidth, low-power designs.

Skills

Full-chip tapeouts
Cross-domain leadership
CPU design/interconnect
Advanced process nodes

Tools

Cadence toolchain

Job description

About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Position Overview

You’ll be the SoC Lead who owns integration of the full chip, or a major module or subsystem, for a system built around a bandwidth problem most digital teams never face. This is a breadth role: you’ll make and defend decisions across DFT, power, timing, and interconnect architecture, with the tapeout scars to know where those decisions bite later. You’ll work closely with System Architects, RTL, physical design, and verification leads to close on system-level tradeoffs, and you’ll help us scale the design org by hiring and mentoring the specialists under you.

Location

Austin, TX or San Jose, CA. Full-time onsite position.

Key Responsibilities
  • Lead integration of the full chip, or a major module/subsystem, including ownership of top-level integration flows.

  • Make and own cross-domain technical decisions spanning system functionality, DFT, power, timing, and interconnect/data-fabric architecture.

  • Partner across microarchitecture, RTL, physical design, verification, and DFT to resolve system-level tradeoffs.

  • Go deep on any domain when needed, staying hands-on with the flow at every level.

  • Help scale the design org: hire, mentor, and grow engineers across specialty domains (subsystem roles are open now and will continue to open).

  • Represent chip-level architecture in the context of advanced-node, high-speed, high-bandwidth, low-power, physically large designs.

Qualifications
  • Principal-level (or equivalent) technical leadership experience at a semiconductor or systems company, with multiple full-chip tapeouts.

  • Demonstrated breadth across domains: for example, you’ve closed timing on a block and argued interconnect architecture in the same design cycle.

  • Deep experience in at least one of: CPU design, or high-speed interconnect / data-fabric design. Interconnect and data-fabric work is especially central to what we’re building.

  • Experience with advanced process nodes, high-bandwidth I/O, and large, physically big subsystem or full-chip designs.

Preferred Skills
  • Cadence toolchain experience.

  • Comfortable being evaluated as either an individual-contributor technical leader or a people manager; we’re open to either path for the right person.

  • Familiarity with AI/ML accelerator or large-scale compute workloads, though not required.

  • Familiarity with AI-assisted EDA flows in the Cadence toolchain (e.g., Cerebrus) for synthesis, timing closure, or verification.

What We Offer

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

Benefits

Join a team that invests in your future and your well-being. At Neurophos, we offer:

  • 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.

  • Unlimited PTO. No rigid vacation banks, just a focus on delivery.

  • 401(k) matching and stock option opportunities to ensure our success is your success.

  • Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.

  • Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Principal SoC Design Engineer / SoC Lead
Principal SoC Design Engineer / SoC Lead

Neurophos • Austin (TX), Sunnyvale (CA)

On-site
USD 180,000 - 240,000
100% coverage of base health plan for你
Unlimited PTO
401(k) matching and stock options
+1
Physical Design / Implementation Lead
Physical Design / Implementation Lead

Neurophos • Austin (TX), Sunnyvale (CA)

On-site
USD 200,000 - 260,000
Health insurance
Unlimited PTO
401(k) matching
+2
Physical Design / Implementation Lead
Physical Design / Implementation Lead

Neurophos, Inc. • Town of Texas (WI), Northern (KY)

Hybrid
USD 180,000 - 240,000
100% health plan premiums for you and/
Unlimited PTO
401(k) matching and stock options
+2
Physical Design / Implementation Lead
Physical Design / Implementation Lead

Neurophos • San Mateo (CA)

On-site
USD 190,000 - 320,000
Health coverage
Unlimited PTO
401(k) matching & stock options
+2
VP of Systems
VP of Systems

Neurophos Inc. • Sunnyvale (CA), Northern (KY)

Hybrid
USD 260,000 - 420,000
Health coverage
Unlimited PTO
Stock options
+2
Lead Security Engineer
Lead Security Engineer

Neurophos Inc. • Sunnyvale (TX), Northern (KY)

Hybrid
USD 180,000 - 240,000
100% health plan premiums coverage
HSA contributions
Unlimited PTO
+3
Principal Platform Security Architect
Principal Platform Security Architect

Socket.dev • Sunnyvale (CA)

On-site
USD 180,000 - 240,000
Principal Platform Security Architect
Principal Platform Security Architect

Neurophos • Austin (TX)

On-site
USD 150,000 - 210,000
Health plan premiums covered
HSA contributions
Unlimited PTO
+2
Firmware Engineer
Firmware Engineer

Neurophos • Austin (TX)

On-site
USD 110,000 - 150,000
Health plan
Unlimited PTO
401(k) matching
+2
Principal Analog Design Engineer
Principal Analog Design Engineer

Neurophos • Austin (TX)

On-site
USD 180,000 - 260,000
100% coverage of health plan premiums
Unlimited PTO
401(k) matching
+2