Silicon Verification Engineer (SystemVerilog, ABV)

MatX; Mountain View (CA); Sur place; USD 160 000 - 600 000; Plein temps

Avantages offerts par ce poste

PTO 4 weeks

Company holidays

Remote work up to 3 weeks

Health insurance

401K up to 5%

Life insurance

Résumé du poste

MatX is hiring silicon verification engineers to build best-in-class silicon for high-performance GenAI. You will contribute to scalable verification across blocks and fullchip, owning verification at subsystem and chip level and delivering tests and coverage closure.

You will work with SystemVerilog, Python, C/C++, Bluespec and ABV/UVM in a fast-paced environment. Prior silicon bring-up and debugging experience is a plus.

Qualifications

• Concept-to-silicon experience driving verification from architecture/specifications to production silicon.
• Proficient in SystemVerilog, Python, C/C++, Bluespec for verification and silicon modeling.
• Experience with UVM and ABV; comfortable with formal and simulated verification.
• Able to create portable tests and drivers for silicon validation and post-silicon debug.
• Strong understanding of micro-architecture in high-performance compute and memory systems.

Responsabilités

• Contribute to verification methodology with scalable solutions across blocks, subsystems, fullchip and system-level validation.
• Own portions of verification execution at subsystem and chip level; create tests and artifacts toclose coverage.
• Plan and drive reviews on verification plans, progress and closure toward tapeout milestones.

Connaissances

SystemVerilog

Python

C/C++

Bluespec

UVM

ABV

Formal verification

Testbenches

Chip bring-up

Description du poste

MatX is hiring silicon verification engineers to build best-in-class silicon for high-performance GenAI. You will contribute to scalable verification across blocks and fullchip, owning verification at subsystem and chip level and delivering tests and coverage closure.

You will work with SystemVerilog, Python, C/C++, Bluespec and ABV/UVM in a fast-paced environment. Prior silicon bring-up and debugging experience is a plus.