Silicon Verification Engineer (SystemVerilog, ABV)

MatX

Mountain View (CA)

On-site

USD 160,000 - 600,000

Full time

31 hours ago
Be an early applicant

Get more replies from employers

Send a job-specific resume in minutes.

Benefits offered by this job

PTO 4 weeks
Company holidays
Remote work up to 3 weeks
Health insurance
401K up to 5%
Life insurance

Job summary

MatX is hiring silicon verification engineers to build best-in-class silicon for high-performance GenAI. You will contribute to scalable verification across blocks and fullchip, owning verification at subsystem and chip level and delivering tests and coverage closure.

You will work with SystemVerilog, Python, C/C++, Bluespec and ABV/UVM in a fast-paced environment. Prior silicon bring-up and debugging experience is a plus.

Qualifications

  • Concept-to-silicon experience driving verification from architecture/specifications to production silicon.
  • Proficient in SystemVerilog, Python, C/C++, Bluespec for verification and silicon modeling.
  • Experience with UVM and ABV; comfortable with formal and simulated verification.
  • Able to create portable tests and drivers for silicon validation and post-silicon debug.
  • Strong understanding of micro-architecture in high-performance compute and memory systems.

Responsibilities

  • Contribute to verification methodology with scalable solutions across blocks, subsystems, fullchip and system-level validation.
  • Own portions of verification execution at subsystem and chip level; create tests and artifacts toclose coverage.
  • Plan and drive reviews on verification plans, progress and closure toward tapeout milestones.

Skills

SystemVerilog
Python
C/C++
Bluespec
UVM
ABV
Formal verification
Testbenches
Chip bring-up

Job description

MatX is hiring silicon verification engineers to build best-in-class silicon for high-performance GenAI. You will contribute to scalable verification across blocks and fullchip, owning verification at subsystem and chip level and delivering tests and coverage closure.

You will work with SystemVerilog, Python, C/C++, Bluespec and ABV/UVM in a fast-paced environment. Prior silicon bring-up and debugging experience is a plus.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Silicon Verification Engineer — Remote-Friendly AI Compute
Silicon Verification Engineer — Remote-Friendly AI Compute

MatX Inc. • Mountain View (CA)

Hybrid
USD 250,000 - 600,000
4 weeks PTO
Holidays
Up to 3 weeks remote work
+1
SoC Design Verification Engineer | Remote Options + Equity
SoC Design Verification Engineer | Remote Options + Equity

MatX • Mountain View (CA)

Hybrid
USD 160,000 - 600,000
4 weeks PTO
12 holidays
Up to 3 weeks remote work
+10
Lead Silicon Bring-Up & Validation Engineer
Lead Silicon Bring-Up & Validation Engineer

Doist • Mountain View (CA)

On-site
USD 170,000 - 475,000
Health insurance
Paid time off
Parental leave
+3
Silicon Validation Engineer — Hybrid, Equity & Benefits
Silicon Validation Engineer — Hybrid, Equity & Benefits

MatX Inc. • Mountain View (CA)

Hybrid
USD 160,000 - 600,000
4 weeks PTO (accrued)
12 company holidays
Up to 3 weeks remote work
+1
Silicon Verification Engineer — UVM, SystemVerilog & C++
Silicon Verification Engineer — UVM, SystemVerilog & C++

Advanced Micro Devices • San Jose (CA), Northern (KY)

Hybrid
USD 150,000 - 190,000
AMD benefits
Senior Silicon Microarchitecture Engineer
Senior Silicon Microarchitecture Engineer

MatX • Mountain View (CA)

Hybrid
USD 120,000 - 600,000
Health, Dental, Vision, and Life insurance
4 weeks paid time off
401(k) with 5% company contribution
+3
Hybrid SOC Micro-Architect & RTL Design Engineer
Hybrid SOC Micro-Architect & RTL Design Engineer

MatX • Mountain View (WY)

On-site
USD 120,000 - 600,000
Equity
Health insurance
Paid time off
+6
SoC Design Verification Engineer
SoC Design Verification Engineer

MatX • Mountain View (CA)

Hybrid
USD 160,000 - 600,000
4 weeks PTO
12 holidays
Up to 3 weeks remote work
+10
Silicon Design Verification Engineer - UVM & SystemVerilog
Silicon Design Verification Engineer - UVM & SystemVerilog

AMD • San Jose (CA)

On-site
USD 120,000 - 190,000
Silicon Design Verification Engineer - UVM & SystemVerilog
Silicon Design Verification Engineer - UVM & SystemVerilog

AMD • United States

On-site
USD 120,000 - 180,000
AMD benefits at a glance