Senior Power Engineer for High-Performance CPU Architecture

SiFive; Santa Clara (CA); Sur place; USD 179 000 - 219 000; Plein temps

Avantages offerts par ce poste

Healthcare

Retirement plans

Paid time off

Résumé du poste

SiFive is seeking a power analytics specialist in California to collect and optimize IP power consumption across design teams. You will guide architecture and design choices to reach state-of-the-art power efficiency, and correlate power models with RTL and silicon.

The role requires 5+ years in power benchmarking/analysis, with experience spanning architecture, logic, and circuit levels; familiarity with ASIC power analysis and optimization; and HW or SW development expertise.

Qualifications

• MS or PhD in Computer Science / Computer Architecture.
• 5+ years of experience in power benchmarking, analysis and modeling.
• Experience with power impacts at architecture, logic design, and circuit levels.
• Good knowledge of computer architecture of high performance out-of-order CPU designs.
• Working experience in guiding trade-off between performance and power to arrive at optimal design.
• Experience with ASIC power analysis and optimization.
• Hands-on expertise with either HW development (RTL/implementation flows, verification/validation,backend flows, FPGA flows) or SW development is a strong plus.
• Self-starter, fast learner, strong problem-solving skills.

Responsabilités

• Collect / analyze SiFive IP power consumption.
• Guide architecture and design to optimize our design to achieve state‑of‑the‑art power efficiency
• Correlate power models with RTL and Silicon
• Innovate ways to improve power analysis flows

Connaissances

Power benchmarking

Power analysis

Power modeling

ASIC power analysis

HW development

SW development

Problem solving

Formation

MS or PhD in Computer Science / Computer Architecture

Outils

RTL/implementation flows

Verification/validation

Backend flows

FPGA flows

Description du poste

SiFive is seeking a power analytics specialist in California to collect and optimize IP power consumption across design teams. You will guide architecture and design choices to reach state-of-the-art power efficiency, and correlate power models with RTL and silicon.

The role requires 5+ years in power benchmarking/analysis, with experience spanning architecture, logic, and circuit levels; familiarity with ASIC power analysis and optimization; and HW or SW development expertise.