SoC Power Analysis Engineer

Infobahn Softworld Inc; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Infobahn Softworld Inc in Irvine, CA is seeking an experienced power IC engineer to drive low-power verification and sign-off processes. The role requires 6+ years and hands-on tool experience.

You will work with Design, DV and Architecture to define low-power vectors, generate data with PTPX, PowerArtist, Calypto, and optimize for PPA, with scripting in Shell/TCL/Perl/Python and exposure to EMIR, Redhawk and RHSC.

Qualifications

• 6+ years of experience in power/low-power verification.
• Define and verify low-power vectors with design, DV, and arch teams.
• Generate early and sign-off power data using PTPX or other low-power tools.
• Analyze power data and optimize for low power to improve PPA.

Responsibilities

• Define and verify low power vectors with the Design, DV, and Architecture teams.
• Generate early (PTPX, PowerArtist, Calypto) and signoff power data using PTPX or any other low power tool.
• Analyze power data, and work with PD and design to optimize for low power and improve PPA.
• Support in enhancing low power flows, and coordinate with tool vendors on power-related issues.
• Hands-on scripting in Shell/TCL/Perl/Python.
• Experience correlating pre-silicon power estimates with post-silicon measurements is a plus.
• Running EMIR on chip level is a big boost; Redhawk and RHSC experience preferred.

Skills

Power estimation

Low power optimization

Scripting: Shell/TCL/Perl/Python

Tools

PTPX

Prime Power

Calypto

PowerArtist

Redhawk

RHSC

Job description

Location: Irvine, San Diego, San Jose – CA (Any one)

Top Skill: PTPX, Prime Power, Calypto. Can run power estimation for whole chip.

• Atleast 6 plus years of experience
• Work closely with the Design, DV, Arch to define and verify low power vectors.
• Generate early (PPRTL, PowerArtist, Calypto) and signoff power data using PTPX or any other low power tool.
• Analyze power data, and work closely with PD and design team to optimize for low power and improve overall PPA.
• Support in enhancing low power flows, work with tool vendors to address any power-related tool or flow issues.
• Hands-on skills in one of the scripting languages, Shell/TCL/Perl/Python
• Experience with correlating pre-silicon power estimates with post-silicon measurements is plus
• Running EMIR on Chip level will be a big boost as well, Redhawk and RHSC experience preferred.