Senior Signoff CAD Engineer - EMIR & SoC Verification

Apple Inc.; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

Apple Inc. seeks a seasoned Signoff Engineer to verify complex mixed-signal designs before tapeout. Lead signoff for IR, EM, and power analyses, while driving AI/ML–assisted flow improvements and enabling cross-team collaboration across Design and CAD groups.

The role emphasizes defining early signoff requirements, hands-on analysis, and supporting front-line requests to ensure robust silicon. Five-figure to six-figure compensation targeted.

Qualifications

• BS in Electrical Engineering or related field required.
• 10+ years of industry experience preferred.
• Experience with mixed-signal verification and signoff.
• Experience CAD and EMIR analysis at transistor/gate level.

Responsibilities

• Define and refine signoff methodologies across gate and transistor levels.
• Ensure signoff criteria are met before tapeout.
• Collaborate with Design, CAD and Technology teams to validate EDA flows.
• Provide frontline enablement, enhancement and debug support.
• Support AI/ML/LLM-driven signoff data analysis and flow automation.

Skills

EMIR analysis

CAD flows

Python scripting

AI/ML in EDA

CMOS analog

LLM tools

Education

BS in EE or related field

Tools

Redhawk

Voltus

Totem

Job description

Apple Inc. seeks a seasoned Signoff Engineer to verify complex mixed-signal designs before tapeout. Lead signoff for IR, EM, and power analyses, while driving AI/ML–assisted flow improvements and enabling cross-team collaboration across Design and CAD groups.

The role emphasizes defining early signoff requirements, hands-on analysis, and supporting front-line requests to ensure robust silicon. Five-figure to six-figure compensation targeted.