Signoff CAD Engineer - Power/EMIR Analysis

Apple Inc.; Austin (TX); On-site; USD 185,000 - 278,000; Full time

Benefits offered by this job

Employee stock plans

Discretionary bonuses

Relocation assistance

Job summary

Apple Inc. in Austin, TX seeks a Signoff Engineer to validate complex mixed-signal designs and drive signoff methodologies from gate to transistor level.

You’ll collaborate with CAD, Design, and Technology teams to ensure readiness before tapeout and enablement across the EDA flow. You should bring a BS in engineering with 3+ years in CAD/EMIR or related roles; experience with Redhawk, Voltus, Totem is preferred and scripting skills are a plus.

Qualifications

• BS in a relevant engineering field.
• 3+ years of industry experience in CAD, EMIR analysis or related circuit design roles.

Responsibilities

• Perform signoff verification and analysis for mixed-signal designs prior to tapeout.
• Define and refine signoff methodologies at gate and transistor levels; support AI/ML driven signoff debugging.

Skills

CAD

EMIR analysis

Circuit design

Education

Bachelor's degree

Tools

Redhawk

Voltus

Totem

Job description

Apple Inc. in Austin, TX seeks a Signoff Engineer to validate complex mixed-signal designs and drive signoff methodologies from gate to transistor level.

You’ll collaborate with CAD, Design, and Technology teams to ensure readiness before tapeout and enablement across the EDA flow. You should bring a BS in engineering with 3+ years in CAD/EMIR or related roles; experience with Redhawk, Voltus, Totem is preferred and scripting skills are a plus.