Senior CAD Signoff Engineer - AI-Powered SoC EMIR

Apple Inc.; Austin (TX); On-site; USD 216,000 - 325,000; Full time

Benefits offered by this job

Stock programs

Employee stock purchase plan

Medical and dental coverage

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. is seeking a Signoff Engineer in the Silicon Technologies group to design and verify advanced SoC signoff methods for high-performance processors. You will work on gate and transistor level analyses, power and signal EM analysis, and AI/ML-driven signoff optimization.

The role involves collaboration with Design, CAD, and Technology teams to ensure proper EDA tool setups and signoff criteria are met before tapeout, with opportunities for growth within Apple’s technology stack.

Qualifications

• BS in Electrical Engineering or related field (required).
• 10+ years of relevant industry experience.
• Experience with signoff for mixed-signal designs and EMIR analysis.

Responsibilities

• Define signoff requirements early in the project lifecycle.
• Collaborate with Design, CAD, and Technology teams to ensure EDA flows are set up.
• Provide frontline support for enablement, enhancement, and debugging requests.
• Interface with design groups to ensure signoff criteria are met by project close.

Skills

EMIR analysis

Signoff methodology

CAD flows

Scripting: Python/Perl

CMOS analog mixed-signal design

Excellent communication

Education

BS in Electrical Engineering or related field

Tools

Redhawk

Voltus

Totem

Job description

Apple Inc. is seeking a Signoff Engineer in the Silicon Technologies group to design and verify advanced SoC signoff methods for high-performance processors. You will work on gate and transistor level analyses, power and signal EM analysis, and AI/ML-driven signoff optimization.

The role involves collaboration with Design, CAD, and Technology teams to ensure proper EDA tool setups and signoff criteria are met before tapeout, with opportunities for growth within Apple’s technology stack.