Senior Signal Integrity Engineer - PAM4 SerDes 200G

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 174,000 - 353,000; Full time

Benefits offered by this job

Health & Wellbeing

Personal & Professional Development

Unconditional Inclusion

Job summary

Hewlett Packard Enterprise Development LP in California is seeking a Senior Signal Integrity Engineer to join our onsite team. The role centers on COM/channel margin analysis, ASIC PAM4 SerDes modeling, and correlating simulations with measurements across packages, boards and connectors.

You will design PCB timing rules, tune SerDes channels up to 200G, perform DVT measurements, and collaborate with vendors to improve model accuracy. Advanced PAM4 experience and CAD tools are required.

Qualifications

• Typically 10+ years of Signal Integrity analysis with a bachelor’s degree in Electrical/Computer/Microwave/RF engineering.
• Typically 8+ years with a master’s degree in the same fields.
• Experience with 56G/112G ASIC PAM4 SerDes technologies is required.
• 200G ASIC PAM4 experience desired.
• Hands-on experience in serial channels up to 200G rates for tuning and TP1A measurements.

Responsibilities

• Perform COM (channel margin) analysis to balance ASIC package, board, and connector trade-offs.
• Develop ASIC PAM4 SerDes channel models and correlate to test structures.
• Correlate PAM4 SerDes simulations with measurements and work with vendors to improve model accuracy.
• Perform PCB timing analysis and define/ document SI design rules and checklists.
• Tune ASIC PAM4 SerDes parameters to improve margins on serial links.
• Perform SI DVT measurements on boards and compare with simulations.
• Provide technical assessments to SI management.

Skills

Channel margin analysis

PAM4 SerDes knowledge

PCB timing analysis

Cross-functional collaboration

Lab debugging

Education

Bachelor’s degree in EE/CE/Microwave/RF

Master’s degree in EE/CE/Microwave/RF

Tools

Ansys HFSS

SIwave

ADS

Allegro

Sigrity

MATLAB

Job description

Hewlett Packard Enterprise Development LP in California is seeking a Senior Signal Integrity Engineer to join our onsite team. The role centers on COM/channel margin analysis, ASIC PAM4 SerDes modeling, and correlating simulations with measurements across packages, boards and connectors.

You will design PCB timing rules, tune SerDes channels up to 200G, perform DVT measurements, and collaborate with vendors to improve model accuracy. Advanced PAM4 experience and CAD tools are required.