Principal Signal Integrity Engineer

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 181,000 - 367,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Principal Signal Integrity Engineer to join an onsite team in California. You will work on high-speed ASIC PAM4 SerDes and system‑level signal and power integrity analyses for advanced networking products.

Responsibilities include channel margin analysis, model development, and coordinating with ASIC vendors to improve accuracy. You will also perform PCB timing analysis, SI rule documentation, and SerDes parameter tuning to boost design margins.

Qualifications

• 10+ years of Signal Integrity analysis experience with a relevant engineering degree.
• 8+ years of SI experience with a Master’s degree in EE/CE/Microwave/RF.
• Experience with 56G/112G ASIC PAM4 SerDes technologies is required.
• 200G PAM4 experience desired.

Responsibilities

• Perform COM (channel margin) analysis to trade off ASIC package, board, and connectors; develop PAM4 SerDes channel models and correlate to test structures.
• Correlate PAM4 SerDes simulation results with measurements and improve models with vendors.
• Perform PCB timing analysis and enforce all SI rules with board engineers and layout designers.
• ASIC PAM4 SerDes parametric tuning to improve design margins.
• Perform SIDVT measurements on boards and correlate simulations with DVT measurements.

Skills

Signal Integrity

SerDes

Channel analysis

PCB timing

Education

Bachelor's in Electrical/Computer/Microwave/RF

Master's in Electrical/Computer/Microwave/RF

Tools

Ansys HFSS

SIwave

Allegro

Sigrity

MATLAB

Job description

Principal Signal Integrity Engineer

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.Our culture thrives onfinding new and better ways to accelerate what’s next.We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.Open up opportunities with HPE.

Job Description:

Work with an experienced signal integrity team with many years of experience performing high speed ASIC PAM4 SerDes and system-level signal and power Integrity analysis for cutting edge networking product design.

Team members are industry experts with hands‑on experience with high-speed ASIC PAM4 SerDes, channel analysis, clocking, I/O timing, on-die power integrity, system-level power integrity, CPM model and PDN optimization, PCB design for SI and PI.

Key Responsibilities:

• Perform COM (channel margin analysis) to provide design trade-offs amongst ASIC package,board, and connectors. Develop ASIC PAM4 SerDes channel simulation models and correlate totest structures.
• Correlate ASIC PAM4 SerDes simulation results with Measurements and work with component and ASIC vendors to improve model accuracy.
• Perform PCB timing analysis, work with board engineersand layout designers to implement all design SI rules, develop and document all layout/SI design rules and checklists.
• ASIC PAM4 SerDes parametric tuning to improve design margins of serial links.
• PerformSIDVTmeasurementsonboardsandcorrelatesimulationswithDVTmeasurements.Provide technical assessment of projects to SI management team.

Basic Requirements:

• Typically, 10 + years of Signal Integrity analysis experience with a Bachelor’s degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering.
• Typically, 8 + years of Signal Integrity analysis experience with a Master’s degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering.
• Experience with 56G/112G ASIC PAM4 SerDes technologies is required.
• 200G ASIC PAM4 experience desired.
• Hands‑on experience in serial channels up to 200G line rates for coefficient tuning, TP1A measurements.

Preferred Skills:

• Proficient with CADtools such as AnsysHFSS, SIwaveADS, Allegro, Sigrity and MATLAB.
• Proficient with lab equipment such as oscilloscopes, Vector Network Analyzers,Time Domain Reflectometers, Spectrum Analyzers, phase noise Analyzers.Good lab debug skills a plus.
• Strong capabilities to debug and provide solutions for ASIC PAM4 SerDes and channel performance issues.
• Design implementation for system clocks and solid understanding of PLL design and debug.
• PCB Stack-up design using 2‑d field solvers.

Knowledge and Skills:

• Good oral and written communication skills.
• Team player able to collaborate withpeople across geography and in a matrix organization.
• Capable of workingon several projects simultaneously.

Accessibility

HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here.

Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Job:

Engineering

Job Level:

TCP_05

The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 181,000 - 367,000 in California
The listed salary range reflects base salary. Variable incentives may also be offered.

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.