Senior PAM4 SerDes & Signal Integrity Architect

Hewlett Packard Enterprise Company; Sunnyvale (CA); On-site; USD 181,000 - 367,000; Full time

Job summary

Hewlett Packard Enterprise seeks a Principal Signal Integrity Engineer to join an experienced SI team in Sunnyvale, CA. You will analyze high-speed ASIC PAM4 SerDes and system-level SI for cutting-edge networking products, driving design trade-offs across ASIC, board, and connectors.

You will work with CAD tools (HFSS, SIwave, ADS, Allegro, Sigrity, MATLAB) and lab equipment to ensure robust signal and power integrity across channels up to 200G.

Qualifications

• Typically 10+ years of SI analysis with a relevant engineering degree.
• Typically 8+ years with a master's degree in related fields.
• Experience with 56G/112G ASIC PAM4 SerDes required.
• Hands-on experience with up to 200G serial channels and TP1A measurements.

Responsibilities

• Perform channel margin analysis to trade off ASIC package, board and connectors.
• Develop PAM4 SerDes channel models and correlate with test structures.
• Correlate simulations with measurements and improve model accuracy.
• Perform PCB timing analysis and document SI design rules.
• TTuning SerDes parameters to improve design margins and perform DVT measurements.

Skills

Signal Integrity

High-speed design

Team collaboration

Education

Bachelor's degree in Electrical Engineering or related

Master's degree in Electrical Engineering or related

Tools

Ansys HFSS

SIwave

ADS

Allegro

Sigrity

MATLAB

Job description

Hewlett Packard Enterprise seeks a Principal Signal Integrity Engineer to join an experienced SI team in Sunnyvale, CA. You will analyze high-speed ASIC PAM4 SerDes and system-level SI for cutting-edge networking products, driving design trade-offs across ASIC, board, and connectors.

You will work with CAD tools (HFSS, SIwave, ADS, Allegro, Sigrity, MATLAB) and lab equipment to ensure robust signal and power integrity across channels up to 200G.